/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
Thumb2RegisterInfo.h | 38 unsigned PredReg = 0,
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Thumb2InstrInfo.cpp | 55 unsigned PredReg = 0; 56 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg); 103 unsigned PredReg = 0; 104 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; 177 ARMCC::CondCodes Pred, unsigned PredReg, 192 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 199 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 208 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 214 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 400 unsigned PredReg; [all...] |
Thumb2InstrInfo.h | 73 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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Thumb2RegisterInfo.cpp | 40 ARMCC::CondCodes Pred, unsigned PredReg,
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ARMLoadStoreOptimizer.cpp | 92 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch, 104 unsigned PredReg, 110 ARMCC::CondCodes Pred, unsigned PredReg, 293 unsigned PredReg, unsigned Scratch, DebugLoc dl, 346 .addImm(Pred).addReg(PredReg).addReg(0); 357 .addImm(Pred).addReg(PredReg); 373 ARMCC::CondCodes Pred, unsigned PredReg, 408 Pred, PredReg, Scratch, dl, Regs)) 440 ARMCC::CondCodes Pred, unsigned PredReg, 493 Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges) [all...] |
Thumb1RegisterInfo.h | 43 unsigned PredReg = 0,
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ARMBaseInstrInfo.h | 338 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 354 ARMCC::CondCodes Pred, unsigned PredReg, 360 ARMCC::CondCodes Pred, unsigned PredReg,
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ARMBaseRegisterInfo.cpp | 804 unsigned PredReg, unsigned MIFlags) const { 814 .addImm(0).addImm(Pred).addReg(PredReg) 838 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 841 Pred, PredReg, TII); 844 Pred, PredReg, TII); 877 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 878 unsigned PredReg = Old->getOperand(2).getReg(); 879 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); 881 // Note: PredReg is operand 3 for ADJCALLSTACKUP. 882 unsigned PredReg = Old->getOperand(3).getReg() [all...] |
MLxExpansionPass.cpp | 219 unsigned PredReg = MI->getOperand(++NextOp).getReg(); 230 MIB.addImm(Pred).addReg(PredReg); 242 MIB.addImm(Pred).addReg(PredReg);
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Thumb2ITBlockPass.cpp | 172 unsigned PredReg = 0; 173 ARMCC::CondCodes CC = llvm::getITInstrPredicate(MI, PredReg);
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ARMBaseRegisterInfo.h | 174 unsigned PredReg = 0,
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Thumb2SizeReduction.cpp | 533 unsigned PredReg = 0; 534 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { 614 unsigned PredReg = 0; 615 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 705 unsigned PredReg = 0; 706 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
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/external/llvm/lib/Target/ARM/ |
ARMLoadStoreOptimizer.cpp | 150 ARMCC::CondCodes Pred, unsigned PredReg); 154 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, 159 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, 460 unsigned PredReg) { 528 .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg); 546 .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg); 596 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, 711 .addImm(Pred).addReg(PredReg); 721 .addImm(Pred).addReg(PredReg); 726 .addImm(Pred).addReg(PredReg); [all...] |
ThumbRegisterInfo.h | 44 unsigned PredReg = 0,
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Thumb2InstrInfo.h | 71 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
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Thumb2InstrInfo.cpp | 60 unsigned PredReg = 0; 61 ARMCC::CondCodes CC = getInstrPredicate(*Tail, PredReg); 108 unsigned PredReg = 0; 109 return getITInstrPredicate(*MBBI, PredReg) == ARMCC::AL; 225 ARMCC::CondCodes Pred, unsigned PredReg, 231 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 248 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 255 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 264 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 275 .addImm((unsigned)Pred).addReg(PredReg).addReg(0 [all...] |
ThumbRegisterInfo.cpp | 66 ARMCC::CondCodes Pred, unsigned PredReg, 78 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg) 86 ARMCC::CondCodes Pred, unsigned PredReg, 106 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { 113 PredReg, MIFlags); 116 PredReg, MIFlags);
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Thumb2ITBlockPass.cpp | 189 unsigned PredReg = 0; 190 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
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Thumb2SizeReduction.cpp | 441 unsigned PredReg = MI->getOperand(5).getReg(); 454 .addReg(PredReg) 647 unsigned PredReg = 0; 648 if (getInstrPredicate(*MI, PredReg) == ARMCC::AL) { 752 unsigned PredReg = 0; 753 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); 848 unsigned PredReg = 0; 849 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg); [all...] |
ARMBaseInstrInfo.h | 454 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg); 476 ARMCC::CondCodes Pred, unsigned PredReg, 483 ARMCC::CondCodes Pred, unsigned PredReg,
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MLxExpansionPass.cpp | 285 unsigned PredReg = MI->getOperand(++NextOp).getReg(); 298 MIB.addImm(Pred).addReg(PredReg); 310 MIB.addImm(Pred).addReg(PredReg);
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ARMBaseRegisterInfo.h | 173 unsigned PredReg = 0,
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
HexagonMCChecker.cpp | 58 unsigned PredReg = Hexagon::NoRegister; 68 PredReg = R; 73 NewPreds.insert(PredReg); 112 Defs[R].insert(PredSense(PredReg, isTrue)); 156 CurDefs.insert(*SRI), Defs[*SRI].insert(PredSense(PredReg, isTrue)); 169 Defs[*SRI].insert(PredSense(PredReg, isTrue)); 185 NewDefs[*SRI].push_back(NewSense::Def(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI), 197 NewDefs[*SRI].push_back(NewSense::Def(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI), 221 NewUses[N] = NewSense::Use(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI)); 564 if (Use.IsNVJ && (Def.IsFloat || Def.PredReg != 0) [all...] |
HexagonMCCompound.cpp | 182 unsigned PredReg = Predicate.getReg(); 184 assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) || 185 (PredReg == Hexagon::P2) || (PredReg == Hexagon::P3)); 192 return (PredReg == Hexagon::P0) ? fp0_jump_nt : fp1_jump_nt; 194 return (PredReg == Hexagon::P0) ? fp0_jump_t : fp1_jump_t; 196 return (PredReg == Hexagon::P0) ? tp0_jump_nt : tp1_jump_nt; 198 return (PredReg == Hexagon::P0) ? tp0_jump_t : tp1_jump_t;
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/external/llvm/lib/Target/Hexagon/ |
HexagonInstrInfo.h | 367 bool predCanBeUsedAsDotNew(const MachineInstr *MI, unsigned PredReg) const; 405 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
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