1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __CCI_400_H__ 32 #define __CCI_400_H__ 33 34 /* Slave interface offsets from PERIPHBASE */ 35 #define SLAVE_IFACE4_OFFSET 0x5000 36 #define SLAVE_IFACE3_OFFSET 0x4000 37 #define SLAVE_IFACE2_OFFSET 0x3000 38 #define SLAVE_IFACE1_OFFSET 0x2000 39 #define SLAVE_IFACE0_OFFSET 0x1000 40 #define SLAVE_IFACE_OFFSET(index) SLAVE_IFACE0_OFFSET + \ 41 (0x1000 * (index)) 42 43 /* Control and ID register offsets */ 44 #define CTRL_OVERRIDE_REG 0x0 45 #define SPEC_CTRL_REG 0x4 46 #define SECURE_ACCESS_REG 0x8 47 #define STATUS_REG 0xc 48 #define IMPRECISE_ERR_REG 0x10 49 #define PERFMON_CTRL_REG 0x100 50 51 /* Slave interface register offsets */ 52 #define SNOOP_CTRL_REG 0x0 53 #define SH_OVERRIDE_REG 0x4 54 #define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100 55 #define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104 56 #define QOS_CTRL_REG 0x10c 57 #define MAX_OT_REG 0x110 58 #define TARGET_LATENCY_REG 0x130 59 #define LATENCY_REGULATION_REG 0x134 60 #define QOS_RANGE_REG 0x138 61 62 /* Snoop Control register bit definitions */ 63 #define DVM_EN_BIT (1 << 1) 64 #define SNOOP_EN_BIT (1 << 0) 65 66 /* Status register bit definitions */ 67 #define CHANGE_PENDING_BIT (1 << 0) 68 69 #ifndef __ASSEMBLY__ 70 71 /* Function declarations */ 72 73 /* 74 * The CCI-400 driver must be initialized with the base address of the 75 * CCI-400 device in the platform memory map, and the cluster indices for 76 * the CCI-400 slave interfaces 3 and 4 respectively. These are the fully 77 * coherent ACE slave interfaces of CCI-400. 78 * The cluster indices must either be 0 or 1, corresponding to the level 1 79 * affinity instance of the mpidr representing the cluster. A negative cluster 80 * index indicates that no cluster is present on that slave interface. 81 */ 82 void cci_init(unsigned long cci_base, 83 int slave_iface3_cluster_ix, 84 int slave_iface4_cluster_ix); 85 86 void cci_enable_cluster_coherency(unsigned long mpidr); 87 void cci_disable_cluster_coherency(unsigned long mpidr); 88 89 #endif /* __ASSEMBLY__ */ 90 #endif /* __CCI_400_H__ */ 91
