| /toolchain/binutils/binutils-2.25/opcodes/ |
| metag-dis.c | 348 dest_no = (insn_word >> 14) & REG_MASK;
372 src_no = (insn_word >> 19) & REG_MASK;
402 dest1_no = (insn_word >> 14) & REG_MASK;
403 dest2_no = (insn_word >> 9) & REG_MASK;
454 src1_no = (insn_word >> 19) & REG_MASK;
455 src2_no = (insn_word >> 14) & REG_MASK;
479 base_no = (insn_word >> 14) & REG_MASK;
531 offset_no = (insn_word >> 9) & REG_MASK;
586 base_no = (insn_word >> 14) & REG_MASK;
602 base_no = (insn_word >> 14) & REG_MASK;
[all...] |
| /external/pcre/dist2/src/sljit/ |
| sljitNativeX86_64.c | 393 if (b & REG_MASK)
398 else if (reg_lmap[b & REG_MASK] == 4)
402 if ((b & REG_MASK) == SLJIT_UNUSED)
405 if (reg_map[b & REG_MASK] >= 8)
415 else if (reg_lmap[b & REG_MASK] == 5)
499 else if ((b & REG_MASK) != SLJIT_UNUSED) {
501 if (immb != 0 || reg_lmap[b & REG_MASK] == 5) {
509 *buf_ptr++ |= reg_lmap[b & REG_MASK];
512 *buf_ptr++ = reg_lmap[b & REG_MASK] | (reg_lmap[OFFS_REG(b)] << 3);
515 if (immb != 0 || reg_lmap[b & REG_MASK] == 5)
[all...] |
| sljitLir.c | 100 #define REG_MASK 0x3f
101 #define OFFS_REG(reg) (((reg) >> 8) & REG_MASK)
102 #define OFFS_REG_MASK (REG_MASK << 8)
105 #define FAST_IS_REG(reg) ((reg) <= REG_MASK)
107 #define SLOW_IS_REG(reg) ((reg) > 0 && (reg) <= REG_MASK)
624 (((exp) & SLJIT_MEM) && (((exp) & REG_MASK) == reg || OFFS_REG(exp) == reg))
713 CHECK_ARGUMENT(FUNCTION_CHECK_IS_REG_OR_UNUSED((p) & REG_MASK)); \
714 CHECK_NOT_VIRTUAL_REGISTER((p) & REG_MASK); \
716 CHECK_ARGUMENT(((p) & REG_MASK) != SLJIT_UNUSED); \
721 CHECK_ARGUMENT(!((p) & ~(SLJIT_MEM | SLJIT_IMM | REG_MASK | OFFS_REG_MASK)));
[all...] |
| sljitNativeX86_32.c | 308 if ((b & REG_MASK) == SLJIT_UNUSED)
318 if ((b & REG_MASK) == SLJIT_SP && !(b & OFFS_REG_MASK))
389 else if ((b & REG_MASK) != SLJIT_UNUSED) {
399 *buf_ptr++ |= reg_map[b & REG_MASK];
402 *buf_ptr++ = reg_map[b & REG_MASK] | (reg_map[OFFS_REG(b)] << 3);
416 *buf_ptr++ = reg_map[b & REG_MASK] | (reg_map[OFFS_REG(b)] << 3) | (immb << 6);
|
| sljitNativeARM_32.c | [all...] |
| sljitNativeARM_64.c | 835 if ((arg & REG_MASK) && !(arg & OFFS_REG_MASK) && argw <= 255 && argw >= -256) {
839 arg &= REG_MASK;
857 | RN(arg & REG_MASK) | RM(OFFS_REG(arg)) | (argw ? (1 << 12) : 0)));
861 arg &= REG_MASK;
891 if (!(arg & REG_MASK)) {
924 if (SLJIT_UNLIKELY((flags & UPDATE) && (arg & REG_MASK))) {
928 other_r = arg & REG_MASK;
968 arg &= REG_MASK;
985 arg &= REG_MASK;
1002 FAIL_IF(push_inst(compiler, ADDI | (1 << 22) | RD(tmp_r) | RN(arg & REG_MASK) | ((argw >> 12) << 10)))
[all...] |
| sljitNativeARM_T2_32.c | 898 if ((arg & REG_MASK) && !(arg & OFFS_REG_MASK) && argw <= 0xff && argw >= -0xff) {
932 if (!(arg & REG_MASK) || argw > 0xfff || argw < -0xff)
984 if (!(arg & REG_MASK)) {
1016 if (SLJIT_UNLIKELY((flags & UPDATE) && (arg & REG_MASK))) {
[all...] |
| sljitNativePPC_common.c | 852 /* Should work when (arg & REG_MASK) == 0. */
864 FAIL_IF(push_inst(compiler, INST_CODE_AND_DST(inst, inp_flags, reg) | A(arg & REG_MASK) | B(OFFS_REG(arg))));
868 if (SLJIT_UNLIKELY(!(arg & REG_MASK)))
873 SLJIT_ASSERT((arg & REG_MASK) || !(inst & UPDATE_REQ));
891 FAIL_IF(push_inst(compiler, INST_CODE_AND_DST(inst, inp_flags, reg) | A(arg & REG_MASK) | IMM(argw)));
926 if (!(arg & REG_MASK))
960 if ((arg & REG_MASK) == tmp_r)
984 return push_inst(compiler, INST_CODE_AND_DST(inst, inp_flags, reg) | A(arg & REG_MASK) | B(tmp_r));
987 if (SLJIT_UNLIKELY(!(arg & REG_MASK)))
991 SLJIT_ASSERT((arg & REG_MASK) || !(inst & UPDATE_REQ))
[all...] |
| sljitNativeX86_common.c | 990 if ((dst & REG_MASK) == SLJIT_R0) {
999 else if ((dst & REG_MASK) == SLJIT_R1)
[all...] |
| sljitNativeSPARC_common.c | 517 if (!(flags & WRITE_BACK) || !(arg & REG_MASK)) {
525 | S1(arg & REG_MASK) | ((arg & OFFS_REG_MASK) ? S2(OFFS_REG(arg)) : IMM(argw)),
567 base = arg & REG_MASK;
[all...] |
| sljitNativeMIPS_common.c | 705 if ((!(flags & WRITE_BACK) || !(arg & REG_MASK)) && !(arg & OFFS_REG_MASK) && argw <= SIMM_MAX && argw >= SIMM_MIN) {
709 FAIL_IF(push_inst(compiler, data_transfer_insts[flags & MEM_MASK] | S(arg & REG_MASK)
759 base = arg & REG_MASK;
[all...] |
| sljitNativeTILEGX_64.c | [all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| gen7_l3_state.c | 187 OUT_BATCH(REG_MASK(HSW_ROW_CHICKEN3_L3_ATOMIC_DISABLE) |
|
| brw_state_upload.c | 405 OUT_BATCH(REG_MASK(GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC) |
|
| brw_defines.h | 51 #define REG_MASK(value) ((value) << 16)
[all...] |
| /external/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| ir-a2xx.c | 38 #define REG_MASK 0x3f
497 assert(num <= REG_MASK);
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-metag.c | [all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| metag.h | [all...] |
