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      1 /* Imagination Technologies Meta opcode table.
      2    Copyright (C) 2013-2014 Free Software Foundation, Inc.
      3    Contributed by Imagination Technologies Ltd.
      4 
      5    This file is part of GDB and GAS.
      6 
      7    GDB and GAS are free software; you can redistribute it and/or
      8    modify it under the terms of the GNU General Public License as
      9    published by the Free Software Foundation; either version 3, or (at
     10    your option) any later version.
     11 
     12    GDB and GAS are distributed in the hope that it will be useful, but
     13    WITHOUT ANY WARRANTY; without even the implied warranty of
     14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     15    General Public License for more details.
     16 
     17    You should have received a copy of the GNU General Public License
     18    along with GDB or GAS; see the file COPYING3.  If not, write to the
     19    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
     20    MA 02110-1301, USA.  */
     21 
     22 enum metag_unit
     23 {
     24   UNIT_CT,
     25   UNIT_D0,
     26   UNIT_D1,
     27   UNIT_A0,
     28   UNIT_A1,
     29   UNIT_PC,
     30   UNIT_RD,
     31   UNIT_TR,
     32   UNIT_TT,
     33   UNIT_FX,
     34   UNIT_DT,			/* DSP Template Table */
     35   UNIT_ACC_D0,
     36   UNIT_ACC_D1,
     37   UNIT_RAM_D0,
     38   UNIT_RAM_D1,
     39 };
     40 
     41 typedef struct
     42 {
     43   const char *     name;
     44   enum metag_unit  unit;
     45   unsigned int     no;
     46 } metag_reg;
     47 
     48 static const metag_reg metag_regtab[] =
     49   {
     50     { "TXENABLE",   UNIT_CT,  0 },
     51     { "CT.0",       UNIT_CT,  0 },
     52     { "TXMODE",     UNIT_CT,  1 },
     53     { "CT.1",       UNIT_CT,  1 },
     54     { "TXSTATUS",   UNIT_CT,  2 },
     55     { "CT.2",       UNIT_CT,  2 },
     56     { "TXRPT",      UNIT_CT,  3 },
     57     { "CT.3",       UNIT_CT,  3 },
     58     { "TXTIMER",    UNIT_CT,  4 },
     59     { "CT.4",       UNIT_CT,  4 },
     60     { "TXL1START",  UNIT_CT,  5 },
     61     { "CT.5",       UNIT_CT,  5 },
     62     { "TXL1END",    UNIT_CT,  6 },
     63     { "CT.6",       UNIT_CT,  6 },
     64     { "TXL1COUNT",  UNIT_CT,  7 },
     65     { "CT.7",       UNIT_CT,  7 },
     66     { "TXL2START",  UNIT_CT,  8 },
     67     { "CT.8",       UNIT_CT,  8 },
     68     { "TXL2END",    UNIT_CT,  9 },
     69     { "CT.9",       UNIT_CT,  9 },
     70     { "TXL2COUNT",  UNIT_CT, 10 },
     71     { "CT.10",      UNIT_CT, 10 },
     72     { "TXBPOBITS",  UNIT_CT, 11 },
     73     { "CT.11",      UNIT_CT, 11 },
     74     { "TXMRSIZE",   UNIT_CT, 12 },
     75     { "CT.12",      UNIT_CT, 12 },
     76     { "TXTIMERI",   UNIT_CT, 13 },
     77     { "CT.13",      UNIT_CT, 13 },
     78     { "TXDRCTRL",   UNIT_CT, 14 },
     79     { "CT.14",      UNIT_CT, 14 },
     80     { "TXDRSIZE",   UNIT_CT, 15 },
     81     { "CT.15",      UNIT_CT, 15 },
     82     { "TXCATCH0",   UNIT_CT, 16 },
     83     { "CT.16",      UNIT_CT, 16 },
     84     { "TXCATCH1",   UNIT_CT, 17 },
     85     { "CT.17",      UNIT_CT, 17 },
     86     { "TXCATCH2",   UNIT_CT, 18 },
     87     { "CT.18",      UNIT_CT, 18 },
     88     { "TXCATCH3",   UNIT_CT, 19 },
     89     { "CT.19",      UNIT_CT, 19 },
     90     { "TXDEFR",     UNIT_CT, 20 },
     91     { "CT.20",      UNIT_CT, 20 },
     92     { "TXCPRS",     UNIT_CT, 21 },
     93     { "CT.21",      UNIT_CT, 21 },
     94     { "TXCLKCTRL",  UNIT_CT, 22 },
     95     { "CT.22",      UNIT_CT, 22 },
     96     { "TXINTERN0",  UNIT_CT, 23 },
     97     { "TXSTATE",    UNIT_CT, 23 },
     98     { "CT.23",      UNIT_CT, 23 },
     99     { "TXAMAREG0",  UNIT_CT, 24 },
    100     { "CT.24",      UNIT_CT, 24 },
    101     { "TXAMAREG1",  UNIT_CT, 25 },
    102     { "CT.25",      UNIT_CT, 25 },
    103     { "TXAMAREG2",  UNIT_CT, 26 },
    104     { "CT.26",      UNIT_CT, 26 },
    105     { "TXAMAREG3",  UNIT_CT, 27 },
    106     { "CT.27",      UNIT_CT, 27 },
    107     { "TXDIVTIME",  UNIT_CT, 28 },
    108     { "CT.28",      UNIT_CT, 28 },
    109     { "TXPRIVEXT",  UNIT_CT, 29 },
    110     { "CT.29",      UNIT_CT, 29 },
    111     { "TXTACTCYC",  UNIT_CT, 30 },
    112     { "TXACTCYC",   UNIT_CT, 30 },
    113     { "CT.30",      UNIT_CT, 30 },
    114     { "TXIDLECYC",  UNIT_CT, 31 },
    115     { "CT.31",      UNIT_CT, 31 },
    116 
    117     { "D0Re0",      UNIT_D0,  0 },
    118     { "D0.0",       UNIT_D0,  0 },
    119     { "D0Ar6",      UNIT_D0,  1 },
    120     { "D0.1",       UNIT_D0,  1 },
    121     { "D0Ar4",      UNIT_D0,  2 },
    122     { "D0.2",       UNIT_D0,  2 },
    123     { "D0Ar2",      UNIT_D0,  3 },
    124     { "D0.3",       UNIT_D0,  3 },
    125     { "D0FrT",      UNIT_D0,  4 },
    126     { "D0.4",       UNIT_D0,  4 },
    127     { "D0.5",       UNIT_D0,  5 },
    128     { "D0.6",       UNIT_D0,  6 },
    129     { "D0.7",       UNIT_D0,  7 },
    130     { "D0.8",       UNIT_D0,  8 },
    131     { "D0.9",       UNIT_D0,  9 },
    132     { "D0.10",      UNIT_D0, 10 },
    133     { "D0.11",      UNIT_D0, 11 },
    134     { "D0.12",      UNIT_D0, 12 },
    135     { "D0.13",      UNIT_D0, 13 },
    136     { "D0.14",      UNIT_D0, 14 },
    137     { "D0.15",      UNIT_D0, 15 },
    138     { "D0.16",      UNIT_D0, 16 },
    139     { "D0.17",      UNIT_D0, 17 },
    140     { "D0.18",      UNIT_D0, 18 },
    141     { "D0.19",      UNIT_D0, 19 },
    142     { "D0.20",      UNIT_D0, 20 },
    143     { "D0.21",      UNIT_D0, 21 },
    144     { "D0.22",      UNIT_D0, 22 },
    145     { "D0.23",      UNIT_D0, 23 },
    146     { "D0.24",      UNIT_D0, 24 },
    147     { "D0.25",      UNIT_D0, 25 },
    148     { "D0.26",      UNIT_D0, 26 },
    149     { "D0.27",      UNIT_D0, 27 },
    150     { "D0.28",      UNIT_D0, 28 },
    151     { "D0.29",      UNIT_D0, 29 },
    152     { "D0.30",      UNIT_D0, 30 },
    153     { "D0.31",      UNIT_D0, 31 },
    154 
    155     { "D1Re0",      UNIT_D1,  0 },
    156     { "D1.0",       UNIT_D1,  0 },
    157     { "D1Ar5",      UNIT_D1,  1 },
    158     { "D1.1",       UNIT_D1,  1 },
    159     { "D1Ar3",      UNIT_D1,  2 },
    160     { "D1.2",       UNIT_D1,  2 },
    161     { "D1Ar1",      UNIT_D1,  3 },
    162     { "D1.3",       UNIT_D1,  3 },
    163     { "D1RtP",      UNIT_D1,  4 },
    164     { "D1.4",       UNIT_D1,  4 },
    165     { "D1.5",       UNIT_D1,  5 },
    166     { "D1.6",       UNIT_D1,  6 },
    167     { "D1.7",       UNIT_D1,  7 },
    168     { "D1.8",       UNIT_D1,  8 },
    169     { "D1.9",       UNIT_D1,  9 },
    170     { "D1.10",      UNIT_D1, 10 },
    171     { "D1.11",      UNIT_D1, 11 },
    172     { "D1.12",      UNIT_D1, 12 },
    173     { "D1.13",      UNIT_D1, 13 },
    174     { "D1.14",      UNIT_D1, 14 },
    175     { "D1.15",      UNIT_D1, 15 },
    176     { "D1.16",      UNIT_D1, 16 },
    177     { "D1.17",      UNIT_D1, 17 },
    178     { "D1.18",      UNIT_D1, 18 },
    179     { "D1.19",      UNIT_D1, 19 },
    180     { "D1.20",      UNIT_D1, 20 },
    181     { "D1.21",      UNIT_D1, 21 },
    182     { "D1.22",      UNIT_D1, 22 },
    183     { "D1.23",      UNIT_D1, 23 },
    184     { "D1.24",      UNIT_D1, 24 },
    185     { "D1.25",      UNIT_D1, 25 },
    186     { "D1.26",      UNIT_D1, 26 },
    187     { "D1.27",      UNIT_D1, 27 },
    188     { "D1.28",      UNIT_D1, 28 },
    189     { "D1.29",      UNIT_D1, 29 },
    190     { "D1.30",      UNIT_D1, 30 },
    191     { "D1.31",      UNIT_D1, 31 },
    192 
    193     { "A0StP",      UNIT_A0,  0 },
    194     { "A0.0",       UNIT_A0,  0 },
    195     { "A0FrP",      UNIT_A0,  1 },
    196     { "A0.1",       UNIT_A0,  1 },
    197     { "A0.2",       UNIT_A0,  2 },
    198     { "A0.3",       UNIT_A0,  3 },
    199     { "A0.4",       UNIT_A0,  4 },
    200     { "A0.5",       UNIT_A0,  5 },
    201     { "A0.6",       UNIT_A0,  6 },
    202     { "A0.7",       UNIT_A0,  7 },
    203     { "A0.8",       UNIT_A0,  8 },
    204     { "A0.9",       UNIT_A0,  9 },
    205     { "A0.10",      UNIT_A0, 10 },
    206     { "A0.11",      UNIT_A0, 11 },
    207     { "A0.12",      UNIT_A0, 12 },
    208     { "A0.13",      UNIT_A0, 13 },
    209     { "A0.14",      UNIT_A0, 14 },
    210     { "A0.15",      UNIT_A0, 15 },
    211     { "CPC0",       UNIT_A0, 16 },
    212 
    213     { "A1GbP",      UNIT_A1,  0 },
    214     { "A1.0",       UNIT_A1,  0 },
    215     { "A1LbP",      UNIT_A1,  1 },
    216     { "A1.1",       UNIT_A1,  1 },
    217     { "A1.2",       UNIT_A1,  2 },
    218     { "A1.3",       UNIT_A1,  3 },
    219     { "A1.4",       UNIT_A1,  4 },
    220     { "A1.5",       UNIT_A1,  5 },
    221     { "A1.6",       UNIT_A1,  6 },
    222     { "A1.7",       UNIT_A1,  7 },
    223     { "A1.8",       UNIT_A1,  8 },
    224     { "A1.9",       UNIT_A1,  9 },
    225     { "A1.10",      UNIT_A1, 10 },
    226     { "A1.11",      UNIT_A1, 11 },
    227     { "A1.12",      UNIT_A1, 12 },
    228     { "A1.13",      UNIT_A1, 13 },
    229     { "A1.14",      UNIT_A1, 14 },
    230     { "A1.15",      UNIT_A1, 15 },
    231     { "CPC1",       UNIT_A1, 16 },
    232 
    233     { "PC",         UNIT_PC,  0 },
    234     { "PCX",        UNIT_PC,  1 },
    235 
    236     { "RD",         UNIT_RD,  0 },
    237     { "RA",         UNIT_RD, 16 },
    238     { "RD",         UNIT_RD, 16 },
    239     { "RAPF",       UNIT_RD, 17 },
    240     { "RAM8X32",    UNIT_RD, 22 },
    241     { "RAM8X",      UNIT_RD, 23 },
    242     { "RABZ",       UNIT_RD, 24 },
    243     { "RAWZ",       UNIT_RD, 25 },
    244     { "RADZ",       UNIT_RD, 26 },
    245     { "RABX",       UNIT_RD, 28 },
    246     { "RAWX",       UNIT_RD, 29 },
    247     { "RADX",       UNIT_RD, 30 },
    248     { "RAMX",       UNIT_RD, 31 },
    249     { "RAM16X",     UNIT_RD, 31 },
    250 
    251     { "TXSTAT",     UNIT_TR,  0 },
    252     { "TR.0",       UNIT_TR,  0 },
    253     { "TXMASK",     UNIT_TR,  1 },
    254     { "TR.1",       UNIT_TR,  1 },
    255     { "TXSTATI",    UNIT_TR,  2 },
    256     { "TR.2",       UNIT_TR,  2 },
    257     { "TXMASKI",    UNIT_TR,  3 },
    258     { "TR.3",       UNIT_TR,  3 },
    259     { "TXPOLL",     UNIT_TR,  4 },
    260     { "TR.4",       UNIT_TR,  4 },
    261     { "TXGPIOI",    UNIT_TR,  5 },
    262     { "TR.5",       UNIT_TR,  5 },
    263     { "TXPOLLI",    UNIT_TR,  6 },
    264     { "TR.6",       UNIT_TR,  6 },
    265     { "TXGPIOO",    UNIT_TR,  7 },
    266     { "TR.7",       UNIT_TR,  7 },
    267 
    268     { "TTEXEC",     UNIT_TT,  0 },
    269     { "TT.0",       UNIT_TT,  0 },
    270     { "TTCTRL",     UNIT_TT,  1 },
    271     { "TT.1",       UNIT_TT,  1 },
    272     { "TTMARK",     UNIT_TT,  2 },
    273     { "TT.2",       UNIT_TT,  2 },
    274     { "TTREC",      UNIT_TT,  3 },
    275     { "TT.3",       UNIT_TT,  3 },
    276     { "GTEXEC",     UNIT_TT,  4 },
    277     { "TT.4",       UNIT_TT,  4 },
    278 
    279     { "FX.0",       UNIT_FX,  0 },
    280     { "FX.1",       UNIT_FX,  1 },
    281     { "FX.2",       UNIT_FX,  2 },
    282     { "FX.3",       UNIT_FX,  3 },
    283     { "FX.4",       UNIT_FX,  4 },
    284     { "FX.5",       UNIT_FX,  5 },
    285     { "FX.6",       UNIT_FX,  6 },
    286     { "FX.7",       UNIT_FX,  7 },
    287     { "FX.8",       UNIT_FX,  8 },
    288     { "FX.9",       UNIT_FX,  9 },
    289     { "FX.10",      UNIT_FX, 10 },
    290     { "FX.11",      UNIT_FX, 11 },
    291     { "FX.12",      UNIT_FX, 12 },
    292     { "FX.13",      UNIT_FX, 13 },
    293     { "FX.14",      UNIT_FX, 14 },
    294     { "FX.15",      UNIT_FX, 15 },
    295   };
    296 
    297 static const metag_reg metag_dsp_regtab[] =
    298   {
    299     { "D0AR.0",   UNIT_RAM_D0,  0 },
    300     { "D0AR.1",   UNIT_RAM_D0,  1 },
    301     { "D0AW.0",   UNIT_RAM_D0,  2 },
    302     { "D0AW.1",   UNIT_RAM_D0,  3 },
    303     { "D0BR.0",   UNIT_RAM_D0,  4 },
    304     { "D0BR.1",   UNIT_RAM_D0,  5 },
    305     { "D0BW.0",   UNIT_RAM_D0,  6 },
    306     { "D0BW.1",   UNIT_RAM_D0,  7 },
    307     { "D0ARI.0",  UNIT_RAM_D0,  8 },
    308     { "D0ARI.1",  UNIT_RAM_D0,  9 },
    309     { "D0AWI.0",  UNIT_RAM_D0, 10 },
    310     { "D0AWI.1",  UNIT_RAM_D0, 11 },
    311     { "D0BRI.0",  UNIT_RAM_D0, 12 },
    312     { "D0BRI.1",  UNIT_RAM_D0, 13 },
    313     { "D0BWI.0",  UNIT_RAM_D0, 14 },
    314     { "D0BWI.1",  UNIT_RAM_D0, 15 },
    315 
    316     { "AC0.0",    UNIT_ACC_D0, 16 },
    317     { "AC0.1",    UNIT_ACC_D0, 17 },
    318     { "AC0.2",    UNIT_ACC_D0, 18 },
    319     { "AC0.3",    UNIT_ACC_D0, 19 },
    320 
    321     { "D1AR.0",   UNIT_RAM_D1,  0 },
    322     { "D1AR.1",   UNIT_RAM_D1,  1 },
    323     { "D1AW.0",   UNIT_RAM_D1,  2 },
    324     { "D1AW.1",   UNIT_RAM_D1,  3 },
    325     { "D1BR.0",   UNIT_RAM_D1,  4 },
    326     { "D1BR.1",   UNIT_RAM_D1,  5 },
    327     { "D1BW.0",   UNIT_RAM_D1,  6 },
    328     { "D1BW.1",   UNIT_RAM_D1,  7 },
    329     { "D1ARI.0",  UNIT_RAM_D1,  8 },
    330     { "D1ARI.1",  UNIT_RAM_D1,  9 },
    331     { "D1AWI.0",  UNIT_RAM_D1, 10 },
    332     { "D1AWI.1",  UNIT_RAM_D1, 11 },
    333     { "D1BRI.0",  UNIT_RAM_D1, 12 },
    334     { "D1BRI.1",  UNIT_RAM_D1, 13 },
    335     { "D1BWI.0",  UNIT_RAM_D1, 14 },
    336     { "D1BWI.1",  UNIT_RAM_D1, 15 },
    337 
    338     { "AC1.0",    UNIT_ACC_D1, 16 },
    339     { "AC1.1",    UNIT_ACC_D1, 17 },
    340     { "AC1.2",    UNIT_ACC_D1, 18 },
    341     { "AC1.3",    UNIT_ACC_D1, 19 },
    342 
    343     { "T0",       UNIT_DT,  0 },
    344     { "T1",       UNIT_DT,  1 },
    345     { "T2",       UNIT_DT,  2 },
    346     { "T3",       UNIT_DT,  3 },
    347     { "T4",       UNIT_DT,  4 },
    348     { "T5",       UNIT_DT,  5 },
    349     { "T6",       UNIT_DT,  6 },
    350     { "T7",       UNIT_DT,  7 },
    351     { "T8",       UNIT_DT,  8 },
    352     { "T9",       UNIT_DT,  9 },
    353     { "TA",       UNIT_DT, 10 },
    354     { "TB",       UNIT_DT, 11 },
    355     { "TC",       UNIT_DT, 12 },
    356     { "TD",       UNIT_DT, 13 },
    357     { "TE",       UNIT_DT, 14 },
    358     { "TF",       UNIT_DT, 15 },
    359   };
    360 
    361 /* This table differs from 'metag_dsp_regtab' in that the number
    362    fields in this table are suitable for insertion into DSPRAM
    363    template definition instruction encodings.
    364 
    365    The table is indexed by "load". The main benefit of this is that we
    366    can implicitly check that the correct DSPRAM register has been used
    367    when parsing, e.g. the read pointer only appears in the load table
    368    and the write pointer only exists in the store table.
    369 
    370    The ordering of the table entries might look a bit weird but it is
    371    based on matching the longest register string. */
    372 static const metag_reg metag_dsp_tmpl_regtab[2][56] =
    373   {
    374     {
    375       { "D0AW.0+D0AWI.0++", UNIT_RAM_D0, 18 },
    376       { "D0AW.0+D0AWI.0",   UNIT_RAM_D0, 18 },
    377       { "D0AW.0+D0AWI.1++", UNIT_RAM_D0, 19 },
    378       { "D0AW.0+D0AWI.1",   UNIT_RAM_D0, 19 },
    379       { "D0AW.0++",         UNIT_RAM_D0, 17 },
    380       { "D0AW.0",           UNIT_RAM_D0, 16 },
    381       { "D0AWI.0",          UNIT_RAM_D0, 18 },
    382       { "D0AWI.1",          UNIT_RAM_D0, 19 },
    383       { "D0AW.1+D0AWI.0++", UNIT_RAM_D0, 22 },
    384       { "D0AW.1+D0AWI.0",   UNIT_RAM_D0, 22 },
    385       { "D0AW.1+D0AWI.1++", UNIT_RAM_D0, 23 },
    386       { "D0AW.1+D0AWI.1",   UNIT_RAM_D0, 23 },
    387       { "D0AW.1++",         UNIT_RAM_D0, 21 },
    388       { "D0AW.1",           UNIT_RAM_D0, 20 },
    389       { "D0BW.0+D0BWI.0++", UNIT_RAM_D0, 26 },
    390       { "D0BW.0+D0BWI.0",   UNIT_RAM_D0, 26 },
    391       { "D0BW.0+D0BWI.1++", UNIT_RAM_D0, 27 },
    392       { "D0BW.0+D0BWI.1",   UNIT_RAM_D0, 27 },
    393       { "D0BW.0++",         UNIT_RAM_D0, 25 },
    394       { "D0BW.0",           UNIT_RAM_D0, 24 },
    395       { "D0BWI.0",          UNIT_RAM_D0, 18 },
    396       { "D0BWI.1",          UNIT_RAM_D0, 19 },
    397       { "D0BW.1+D0BWI.0++", UNIT_RAM_D0, 30 },
    398       { "D0BW.1+D0BWI.0",   UNIT_RAM_D0, 30 },
    399       { "D0BW.1+D0BWI.1++", UNIT_RAM_D0, 31 },
    400       { "D0BW.1+D0BWI.1",   UNIT_RAM_D0, 31 },
    401       { "D0BW.1++",         UNIT_RAM_D0, 29 },
    402       { "D0BW.1",           UNIT_RAM_D0, 28 },
    403 
    404       { "D1AW.0+D1AWI.0++", UNIT_RAM_D1, 18 },
    405       { "D1AW.0+D1AWI.0",   UNIT_RAM_D1, 18 },
    406       { "D1AW.0+D1AWI.1++", UNIT_RAM_D1, 19 },
    407       { "D1AW.0+D1AWI.1",   UNIT_RAM_D1, 19 },
    408       { "D1AW.0++",         UNIT_RAM_D1, 17 },
    409       { "D1AW.0",           UNIT_RAM_D1, 16 },
    410       { "D1AWI.0",          UNIT_RAM_D1, 18 },
    411       { "D1AWI.1",          UNIT_RAM_D1, 19 },
    412       { "D1AW.1+D1AWI.0++", UNIT_RAM_D1, 22 },
    413       { "D1AW.1+D1AWI.0",   UNIT_RAM_D1, 22 },
    414       { "D1AW.1+D1AWI.1++", UNIT_RAM_D1, 23 },
    415       { "D1AW.1+D1AWI.1",   UNIT_RAM_D1, 23 },
    416       { "D1AW.1++",         UNIT_RAM_D1, 21 },
    417       { "D1AW.1",           UNIT_RAM_D1, 20 },
    418       { "D1BW.0+D1BWI.0++", UNIT_RAM_D1, 26 },
    419       { "D1BW.0+D1BWI.0",   UNIT_RAM_D1, 26 },
    420       { "D1BW.0+D1BWI.1++", UNIT_RAM_D1, 27 },
    421       { "D1BW.0+D1BWI.1",   UNIT_RAM_D1, 27 },
    422       { "D1BW.0++",         UNIT_RAM_D1, 25 },
    423       { "D1BW.0",           UNIT_RAM_D1, 24 },
    424       { "D1BWI.0",          UNIT_RAM_D1, 18 },
    425       { "D1BWI.1",          UNIT_RAM_D1, 19 },
    426       { "D1BW.1+D1BWI.0++", UNIT_RAM_D1, 30 },
    427       { "D1BW.1+D1BWI.0",   UNIT_RAM_D1, 30 },
    428       { "D1BW.1+D1BWI.1++", UNIT_RAM_D1, 31 },
    429       { "D1BW.1+D1BWI.1",   UNIT_RAM_D1, 31 },
    430       { "D1BW.1++",         UNIT_RAM_D1, 29 },
    431       { "D1BW.1",           UNIT_RAM_D1, 28 },
    432     },
    433 
    434     {
    435       { "D0AR.0+D0ARI.0++", UNIT_RAM_D0, 18 },
    436       { "D0AR.0+D0ARI.0",   UNIT_RAM_D0, 18 },
    437       { "D0AR.0+D0ARI.1++", UNIT_RAM_D0, 19 },
    438       { "D0AR.0+D0ARI.1",   UNIT_RAM_D0, 19 },
    439       { "D0AR.0++",         UNIT_RAM_D0, 17 },
    440       { "D0AR.0",           UNIT_RAM_D0, 16 },
    441       { "D0ARI.0",          UNIT_RAM_D0, 18 },
    442       { "D0ARI.1",          UNIT_RAM_D0, 19 },
    443       { "D0AR.1+D0ARI.0++", UNIT_RAM_D0, 22 },
    444       { "D0AR.1+D0ARI.0",   UNIT_RAM_D0, 22 },
    445       { "D0AR.1+D0ARI.1++", UNIT_RAM_D0, 23 },
    446       { "D0AR.1+D0ARI.1",   UNIT_RAM_D0, 23 },
    447       { "D0AR.1++",         UNIT_RAM_D0, 21 },
    448       { "D0AR.1",           UNIT_RAM_D0, 20 },
    449       { "D0BR.0+D0BRI.0++", UNIT_RAM_D0, 26 },
    450       { "D0BR.0+D0BRI.0",   UNIT_RAM_D0, 26 },
    451       { "D0BR.0+D0BRI.1++", UNIT_RAM_D0, 27 },
    452       { "D0BR.0+D0BRI.1",   UNIT_RAM_D0, 27 },
    453       { "D0BR.0++",         UNIT_RAM_D0, 25 },
    454       { "D0BR.0",           UNIT_RAM_D0, 24 },
    455       { "D0BRI.0",          UNIT_RAM_D0, 18 },
    456       { "D0BRI.1",          UNIT_RAM_D0, 19 },
    457       { "D0BR.1+D0BRI.0++", UNIT_RAM_D0, 30 },
    458       { "D0BR.1+D0BRI.0",   UNIT_RAM_D0, 30 },
    459       { "D0BR.1+D0BRI.1++", UNIT_RAM_D0, 31 },
    460       { "D0BR.1+D0BRI.1",   UNIT_RAM_D0, 31 },
    461       { "D0BR.1++",         UNIT_RAM_D0, 29 },
    462       { "D0BR.1",           UNIT_RAM_D0, 28 },
    463 
    464       { "D1AR.0+D1ARI.0++", UNIT_RAM_D1, 18 },
    465       { "D1AR.0+D1ARI.0",   UNIT_RAM_D1, 18 },
    466       { "D1AR.0+D1ARI.1++", UNIT_RAM_D1, 19 },
    467       { "D1AR.0+D1ARI.1",   UNIT_RAM_D1, 19 },
    468       { "D1AR.0++",         UNIT_RAM_D1, 17 },
    469       { "D1AR.0",           UNIT_RAM_D1, 16 },
    470       { "D1ARI.0",          UNIT_RAM_D1, 18 },
    471       { "D1ARI.1",          UNIT_RAM_D1, 19 },
    472       { "D1AR.1+D1ARI.0++", UNIT_RAM_D1, 22 },
    473       { "D1AR.1+D1ARI.0",   UNIT_RAM_D1, 22 },
    474       { "D1AR.1+D1ARI.1++", UNIT_RAM_D1, 23 },
    475       { "D1AR.1+D1ARI.1",   UNIT_RAM_D1, 23 },
    476       { "D1AR.1++",         UNIT_RAM_D1, 21 },
    477       { "D1AR.1",           UNIT_RAM_D1, 20 },
    478       { "D1BR.0+D1BRI.0++", UNIT_RAM_D1, 26 },
    479       { "D1BR.0+D1BRI.0",   UNIT_RAM_D1, 26 },
    480       { "D1BR.0+D1BRI.1++", UNIT_RAM_D1, 27 },
    481       { "D1BR.0+D1BRI.1",   UNIT_RAM_D1, 27 },
    482       { "D1BR.0++",         UNIT_RAM_D1, 25 },
    483       { "D1BR.0",           UNIT_RAM_D1, 24 },
    484       { "D1BR.1+D1BRI.0++", UNIT_RAM_D1, 30 },
    485       { "D1BR.1+D1BRI.0",   UNIT_RAM_D1, 30 },
    486       { "D1BR.1+D1BRI.1++", UNIT_RAM_D1, 31 },
    487       { "D1BR.1+D1BRI.1",   UNIT_RAM_D1, 31 },
    488       { "D1BR.1++",         UNIT_RAM_D1, 29 },
    489       { "D1BR.1",           UNIT_RAM_D1, 28 },
    490       { "D1BRI.0",          UNIT_RAM_D1, 18 },
    491       { "D1BRI.1",          UNIT_RAM_D1, 19 },
    492     },
    493   };
    494 
    495 typedef struct
    496 {
    497   const char *  name;
    498   unsigned int  part;
    499 } metag_acf;
    500 
    501 static const metag_acf metag_acftab[] =
    502   {
    503     { "ACF.0", 0},
    504     { "ACF.1", 1},
    505     { "ACF.2", 2},
    506     { "ACF.3", 3},
    507   };
    508 
    509 enum insn_encoding
    510 {
    511   ENC_NONE,
    512   ENC_MOV_U2U,
    513   ENC_MOV_PORT,
    514   ENC_MMOV,
    515   ENC_MDRD,
    516   ENC_MOVL_TTREC,
    517   ENC_GET_SET,
    518   ENC_GET_SET_EXT,
    519   ENC_MGET_MSET,
    520   ENC_COND_SET,
    521   ENC_XFR,
    522   ENC_MOV_CT,
    523   ENC_SWAP,
    524   ENC_JUMP,
    525   ENC_CALLR,
    526   ENC_ALU,
    527   ENC_SHIFT,
    528   ENC_MIN_MAX,
    529   ENC_BITOP,
    530   ENC_CMP,
    531   ENC_BRANCH,
    532   ENC_KICK,
    533   ENC_SWITCH,
    534   ENC_CACHER,
    535   ENC_CACHEW,
    536   ENC_ICACHE,
    537   ENC_LNKGET,
    538   ENC_FMOV,
    539   ENC_FMMOV,
    540   ENC_FMOV_DATA,
    541   ENC_FMOV_I,
    542   ENC_FPACK,
    543   ENC_FSWAP,
    544   ENC_FCMP,
    545   ENC_FMINMAX,
    546   ENC_FCONV,
    547   ENC_FCONVX,
    548   ENC_FBARITH,
    549   ENC_FEARITH,
    550   ENC_FREC,
    551   ENC_FSIMD,
    552   ENC_FGET_SET_ACF,
    553   ENC_DGET_SET,
    554   ENC_DTEMPLATE,
    555   ENC_DALU,
    556   ENC_MAX,
    557 };
    558 
    559 enum insn_type
    560 {
    561   INSN_GP,
    562   INSN_FPU,
    563   INSN_DSP,
    564   INSN_DSP_FPU,
    565 };
    566 
    567 typedef struct
    568 {
    569   const char *name;
    570 
    571   unsigned int core_flags;
    572 #define CoreMeta11             0x1 /* The earliest Meta core we support */
    573 #define CoreMeta12             0x2
    574 #define CoreMeta21             0x4
    575 
    576 #define FpuMeta21             0x21
    577 
    578 #define DspMeta21             0x100
    579 
    580   unsigned int meta_opcode;
    581   unsigned int meta_mask;
    582 
    583   enum insn_type insn_type;
    584 
    585   enum insn_encoding encoding;
    586 
    587 #define DSP_ARGS_1    0x0000001 /* De.r,Dx.r,De.r (3 register operands) */
    588 #define DSP_ARGS_ACC2 0x0000002 /* Accumulator source operand 2 */
    589 #define DSP_ARGS_QR   0x0000004 /* QUICKRoT */
    590 #define DSP_ARGS_XACC 0x0000008 /* Cross-unit accumulator op */
    591 #define DSP_ARGS_DACC 0x0000010 /* Target accumulator as destination */
    592 #define DSP_ARGS_SRD  0x0000020 /* Source the RD port */
    593 #define DSP_ARGS_2    0x0000040 /* De.r,Dx.r (2 register operands) */
    594 #define DSP_ARGS_DSP_SRC1   0x0000080 /* Source a DSP register */
    595 #define DSP_ARGS_DSP_SRC2   0x0000100 /* Source a DSP register */
    596 #define DSP_ARGS_IMM 0x0000200 /* Immediate value for src 2 */
    597 #define DSP_ARGS_SPLIT8  0x0000400 /* Data unit split 8 operations */
    598 #define DSP_ARGS_12  0x0000800 /* De.r,Dx.r */
    599 #define DSP_ARGS_13  0x0001000 /* Dx.r,Rx.r */
    600 #define DSP_ARGS_14  0x0002000 /* DSPe.r,Dx.r */
    601 #define DSP_ARGS_15  0x0004000 /* DSPx.r,#I16 */
    602 #define DSP_ARGS_16  0x0008000 /* De.r,DSPx.r */
    603 #define DSP_ARGS_17  0x0010000 /* De.r|ACe.r,Dx.r,Rx.r|RD */
    604 #define DSP_ARGS_18  0x0020000 /* De.r,Dx.r|ACx.r */
    605 #define DSP_ARGS_20  0x0080000 /* De.r,Dx.r|ACx.r,De.r */
    606 #define DSP_ARGS_21  0x0100000 /* De.r,Dx.r|ACx.r,#I5 */
    607 #define DSP_ARGS_22  0x0200000 /* De.r,Dx.r|ACx.r,De.r|#I5 */
    608 #define DSP_ARGS_23  0x0400000 /* Ux.r,Dx.r|ACx.r,De.r|#I5 */
    609 #define GP_ARGS_QR   0x0000001 /* QUICKRoT */
    610   unsigned int arg_type;
    611 } insn_template;
    612 
    613 enum major_opcode
    614 {
    615   OPC_ADD,
    616   OPC_SUB,
    617   OPC_AND,
    618   OPC_OR,
    619   OPC_XOR,
    620   OPC_SHIFT,
    621   OPC_MUL,
    622   OPC_CMP,
    623   OPC_ADDR,
    624   OPC_9,
    625   OPC_MISC,
    626   OPC_SET,
    627   OPC_GET,
    628   OPC_XFR,
    629   OPC_CPR,
    630   OPC_FPU,
    631 };
    632 
    633 #define GET_EXT_MINOR        0x7
    634 #define MOV_EXT_MINOR        0x6
    635 #define MOVL_MINOR           0x2
    636 
    637 #define MAJOR_OPCODE(opcode) (((opcode) >> 28) & 0xf)
    638 #define MINOR_OPCODE(opcode) (((opcode) >> 24) & 0xf)
    639 
    640 enum cond_code
    641 {
    642   COND_A,
    643   COND_EQ,
    644   COND_NE,
    645   COND_CS,
    646   COND_CC,
    647   COND_MI,
    648   COND_PL,
    649   COND_VS,
    650   COND_VC,
    651   COND_HI,
    652   COND_LS,
    653   COND_GE,
    654   COND_LT,
    655   COND_GT,
    656   COND_LE,
    657   COND_NV,
    658 };
    659 
    660 enum scond_code
    661 {
    662   SCOND_A,
    663   SCOND_LEQ,
    664   SCOND_LNE,
    665   SCOND_LLO,
    666   SCOND_LHS,
    667   SCOND_HEQ,
    668   SCOND_HNE,
    669   SCOND_HLO,
    670   SCOND_HHS,
    671   SCOND_LGR,
    672   SCOND_LLE,
    673   SCOND_HGR,
    674   SCOND_HLE,
    675   SCOND_EEQ,
    676   SCOND_ELO,
    677   SCOND_NV,
    678 };
    679 
    680 typedef struct
    681 {
    682   const char *name;
    683   enum scond_code code;
    684 } split_condition;
    685 
    686 static const split_condition metag_scondtab[] =
    687   {
    688     { "LEQ",   SCOND_LEQ },
    689     { "LEZ",   SCOND_LEQ },
    690     { "LNE",   SCOND_LNE },
    691     { "LNZ",   SCOND_LNE },
    692     { "LLO",   SCOND_LLO },
    693     { "LCS",   SCOND_LLO },
    694     { "LHS",   SCOND_LHS },
    695     { "LCC",   SCOND_LHS },
    696     { "HEQ",   SCOND_HEQ },
    697     { "HEZ",   SCOND_HEQ },
    698     { "HNE",   SCOND_HNE },
    699     { "HNZ",   SCOND_HNE },
    700     { "HLO",   SCOND_HLO },
    701     { "HCS",   SCOND_HLO },
    702     { "HHS",   SCOND_HHS },
    703     { "HCC",   SCOND_HHS },
    704     { "LGR",   SCOND_LGR },
    705     { "LHI",   SCOND_LGR },
    706     { "LLE",   SCOND_LLE },
    707     { "LLS",   SCOND_LLE },
    708     { "HGR",   SCOND_HGR },
    709     { "HHI",   SCOND_HGR },
    710     { "HLE",   SCOND_HLE },
    711     { "HLS",   SCOND_HLE },
    712     { "EEQ",   SCOND_EEQ },
    713     { "EEZ",   SCOND_EEQ },
    714     { "ELO",   SCOND_ELO },
    715     { "ECS",   SCOND_ELO },
    716   };
    717 
    718 static const split_condition metag_dsp_scondtab[] =
    719   {
    720     { "LEQ",   SCOND_LEQ },
    721     { "LEZ",   SCOND_LEQ },
    722     { "LNE",   SCOND_LNE },
    723     { "LNZ",   SCOND_LNE },
    724     { "LCS",   SCOND_LLO },
    725     { "LLO",   SCOND_LLO },
    726     { "LCC",   SCOND_LHS },
    727     { "LHS",   SCOND_LHS },
    728     { "HEQ",   SCOND_HEQ },
    729     { "HEZ",   SCOND_HEQ },
    730     { "HNE",   SCOND_HNE },
    731     { "HNZ",   SCOND_HNE },
    732     { "HCS",   SCOND_HLO },
    733     { "HLO",   SCOND_HLO },
    734     { "HCC",   SCOND_HHS },
    735     { "HHS",   SCOND_HHS },
    736     { "LHI",   SCOND_LGR },
    737     { "LGR",   SCOND_LGR },
    738     { "LLS",   SCOND_LLE },
    739     { "LLE",   SCOND_LLE },
    740     { "HHI",   SCOND_HGR },
    741     { "HGR",   SCOND_HGR },
    742     { "HLS",   SCOND_HLE },
    743     { "HLE",   SCOND_HLE },
    744     { "EEQ",   SCOND_EEQ },
    745     { "EEZ",   SCOND_EEQ },
    746     { "ECS",   SCOND_ELO },
    747     { "ELO",   SCOND_ELO },
    748   };
    749 
    750 static const split_condition metag_fpu_scondtab[] =
    751   {
    752     { "LEQ",   SCOND_LEQ },
    753     { "LEZ",   SCOND_LEQ },
    754     { "LNE",   SCOND_LNE },
    755     { "LNZ",   SCOND_LNE },
    756     { "LLO",   SCOND_LLO },
    757     { "LCS",   SCOND_LLO },
    758     { "LHS",   SCOND_LHS },
    759     { "LCC",   SCOND_LHS },
    760     { "HEQ",   SCOND_HEQ },
    761     { "HEZ",   SCOND_HEQ },
    762     { "HNE",   SCOND_HNE },
    763     { "HNZ",   SCOND_HNE },
    764     { "HLO",   SCOND_HLO },
    765     { "HCS",   SCOND_HLO },
    766     { "HHS",   SCOND_HHS },
    767     { "HCC",   SCOND_HHS },
    768     { "LGR",   SCOND_LGR },
    769     { "LHI",   SCOND_LGR },
    770     { "LLE",   SCOND_LLE },
    771     { "LLS",   SCOND_LLE },
    772     { "HGR",   SCOND_HGR },
    773     { "HHI",   SCOND_HGR },
    774     { "HLE",   SCOND_HLE },
    775     { "HLS",   SCOND_HLE },
    776     { "EEQ",   SCOND_EEQ },
    777     { "EEZ",   SCOND_EEQ },
    778     { "ELO",   SCOND_ELO },
    779     { "ECS",   SCOND_ELO },
    780   };
    781 
    782 enum fcond_code
    783 {
    784   FCOND_A,
    785   FCOND_FEQ,
    786   FCOND_UNE,
    787   FCOND_FLT,
    788   FCOND_UGE,
    789 
    790   FCOND_UVS = 7,
    791   FCOND_FVC,
    792   FCOND_UGT,
    793   FCOND_FLE,
    794   FCOND_FGE,
    795   FCOND_ULT,
    796   FCOND_FGT,
    797   FCOND_ULE,
    798   FCOND_NV,
    799 };
    800 
    801 #define COND_INSN(mnemonic, suffix, field_shift, flags, meta_opcode,	\
    802 		  meta_mask, insn_type,	encoding, args)			\
    803   { mnemonic suffix, flags, meta_opcode, meta_mask,			\
    804       insn_type, encoding, args },					\
    805   { mnemonic "A" suffix, flags, meta_opcode, meta_mask,			\
    806       insn_type, encoding, args },					\
    807   { mnemonic "EQ" suffix, flags, meta_opcode | (COND_EQ << field_shift), \
    808       meta_mask, insn_type, encoding, args },				\
    809   { mnemonic "Z" suffix, flags, meta_opcode | (COND_EQ << field_shift),	\
    810       meta_mask, insn_type, encoding, args },				\
    811   { mnemonic "NE" suffix, flags, meta_opcode | (COND_NE << field_shift), \
    812       meta_mask, insn_type, encoding, args },				\
    813   { mnemonic "NZ" suffix, flags, meta_opcode | (COND_NE << field_shift), \
    814       meta_mask, insn_type, encoding, args },				\
    815   { mnemonic "CS" suffix, flags, meta_opcode | (COND_CS << field_shift), \
    816       meta_mask, insn_type, encoding, args },				\
    817   { mnemonic "LO" suffix, flags, meta_opcode | (COND_CS << field_shift), \
    818       meta_mask, insn_type, encoding, args },				\
    819   { mnemonic "CC" suffix, flags, meta_opcode | (COND_CC << field_shift), \
    820       meta_mask, insn_type, encoding, args },				\
    821   { mnemonic "HS" suffix, flags, meta_opcode | (COND_CC << field_shift), \
    822       meta_mask, insn_type, encoding, args },				\
    823   { mnemonic "MI" suffix, flags, meta_opcode | (COND_MI << field_shift), \
    824       meta_mask, insn_type, encoding, args },				\
    825   { mnemonic "N" suffix, flags, meta_opcode | (COND_MI << field_shift),	\
    826       meta_mask, insn_type, encoding, args },				\
    827   { mnemonic "PL" suffix, flags, meta_opcode | (COND_PL << field_shift), \
    828       meta_mask, insn_type, encoding, args },				\
    829   { mnemonic "NC" suffix, flags, meta_opcode | (COND_PL << field_shift), \
    830       meta_mask, insn_type, encoding, args },				\
    831   { mnemonic "VS" suffix, flags, meta_opcode | (COND_VS << field_shift), \
    832       meta_mask, insn_type, encoding, args },				\
    833   { mnemonic "VC" suffix, flags, meta_opcode | (COND_VC << field_shift), \
    834       meta_mask, insn_type, encoding, args },				\
    835   { mnemonic "HI" suffix, flags, meta_opcode | (COND_HI << field_shift), \
    836       meta_mask, insn_type, encoding, args },				\
    837   { mnemonic "LS" suffix, flags, meta_opcode | (COND_LS << field_shift), \
    838       meta_mask, insn_type, encoding, args },				\
    839   { mnemonic "GE" suffix, flags, meta_opcode | (COND_GE << field_shift), \
    840       meta_mask, insn_type, encoding, args },				\
    841   { mnemonic "LT" suffix, flags, meta_opcode | (COND_LT << field_shift), \
    842       meta_mask, insn_type, encoding, args },				\
    843   { mnemonic "GT" suffix, flags, meta_opcode | (COND_GT << field_shift), \
    844       meta_mask, insn_type, encoding, args },				\
    845   { mnemonic "LE" suffix, flags, meta_opcode | (COND_LE << field_shift), \
    846       meta_mask, insn_type, encoding, args },				\
    847   { mnemonic "NV" suffix, flags, meta_opcode | (COND_NV << field_shift), \
    848       meta_mask, insn_type, encoding, args },				\
    849   { mnemonic "FEQ" suffix, flags, meta_opcode |				\
    850       (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    851   { mnemonic "FZ" suffix, flags, meta_opcode |				\
    852       (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    853   { mnemonic "UNE" suffix, flags, meta_opcode |				\
    854       (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    855   { mnemonic "UNZ" suffix, flags, meta_opcode |				\
    856       (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    857   { mnemonic "FLT" suffix, flags, meta_opcode |				\
    858       (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    859   { mnemonic "FLO" suffix, flags, meta_opcode |				\
    860       (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    861   { mnemonic "UGE" suffix, flags, meta_opcode |				\
    862       (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    863   { mnemonic "UHS" suffix, flags, meta_opcode |				\
    864       (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    865   { mnemonic "UVS" suffix, flags, meta_opcode |				\
    866       (FCOND_UVS << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    867   { mnemonic "FVC" suffix, flags, meta_opcode |				\
    868       (FCOND_FVC << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    869   { mnemonic "UGT" suffix, flags, meta_opcode |				\
    870       (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    871   { mnemonic "UHI" suffix, flags, meta_opcode |				\
    872       (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    873   { mnemonic "FLE" suffix, flags, meta_opcode |				\
    874       (FCOND_FLE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    875   { mnemonic "FGE" suffix, flags, meta_opcode |				\
    876       (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    877   { mnemonic "FHS" suffix, flags, meta_opcode |				\
    878       (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    879   { mnemonic "ULT" suffix, flags, meta_opcode |				\
    880       (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    881   { mnemonic "ULO" suffix, flags, meta_opcode |				\
    882       (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    883   { mnemonic "FGT" suffix, flags, meta_opcode |				\
    884       (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    885   { mnemonic "FHI" suffix, flags, meta_opcode |				\
    886       (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    887   { mnemonic "ULE" suffix, flags, meta_opcode |				\
    888       (FCOND_ULE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    889   { mnemonic "NV" suffix, flags, meta_opcode |				\
    890       (FCOND_NV << field_shift), meta_mask, INSN_FPU, encoding, args }
    891 
    892 #define FCOND_INSN(mnemonic, suffix, field_shift, flags, meta_opcode,	\
    893 		  meta_mask, insn_type,	encoding, args)			\
    894   { mnemonic suffix, flags, meta_opcode, meta_mask,			\
    895       insn_type, encoding, args },					\
    896   { mnemonic "A" suffix, flags, meta_opcode, meta_mask,			\
    897       insn_type, encoding, args },					\
    898   { mnemonic "FEQ" suffix, flags, meta_opcode |				\
    899       (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    900   { mnemonic "FZ" suffix, flags, meta_opcode |				\
    901       (FCOND_FEQ << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    902   { mnemonic "UNE" suffix, flags, meta_opcode |				\
    903       (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    904   { mnemonic "UNZ" suffix, flags, meta_opcode |				\
    905       (FCOND_UNE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    906   { mnemonic "FLO" suffix, flags, meta_opcode |				\
    907       (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    908   { mnemonic "FLT" suffix, flags, meta_opcode |				\
    909       (FCOND_FLT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    910   { mnemonic "UHS" suffix, flags, meta_opcode |				\
    911       (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    912   { mnemonic "UGE" suffix, flags, meta_opcode |				\
    913       (FCOND_UGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    914   { mnemonic "UVS" suffix, flags, meta_opcode |				\
    915       (FCOND_UVS << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    916   { mnemonic "FVC" suffix, flags, meta_opcode |				\
    917       (FCOND_FVC << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    918   { mnemonic "UHI" suffix, flags, meta_opcode |				\
    919       (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    920   { mnemonic "UGT" suffix, flags, meta_opcode |				\
    921       (FCOND_UGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    922   { mnemonic "FLE" suffix, flags, meta_opcode |				\
    923       (FCOND_FLE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    924   { mnemonic "FGE" suffix, flags, meta_opcode |				\
    925       (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    926   { mnemonic "FHS" suffix, flags, meta_opcode |				\
    927       (FCOND_FGE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    928   { mnemonic "ULT" suffix, flags, meta_opcode |				\
    929       (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    930   { mnemonic "ULO" suffix, flags, meta_opcode |				\
    931       (FCOND_ULT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    932   { mnemonic "FGT" suffix, flags, meta_opcode |				\
    933       (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    934   { mnemonic "FHI" suffix, flags, meta_opcode |				\
    935       (FCOND_FGT << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    936   { mnemonic "ULE" suffix, flags, meta_opcode |				\
    937       (FCOND_ULE << field_shift), meta_mask, INSN_FPU, encoding, args }, \
    938   { mnemonic "NV" suffix, flags, meta_opcode |				\
    939       (FCOND_NV << field_shift), meta_mask, INSN_FPU, encoding, args },	\
    940   { mnemonic "EQ" suffix, flags, meta_opcode | (COND_EQ << field_shift), \
    941       meta_mask, insn_type, encoding, args },				\
    942   { mnemonic "Z" suffix, flags, meta_opcode | (COND_EQ << field_shift),	\
    943       meta_mask, insn_type, encoding, args },				\
    944   { mnemonic "NE" suffix, flags, meta_opcode | (COND_NE << field_shift), \
    945       meta_mask, insn_type, encoding, args },				\
    946   { mnemonic "NZ" suffix, flags, meta_opcode | (COND_NE << field_shift), \
    947       meta_mask, insn_type, encoding, args },				\
    948   { mnemonic "CS" suffix, flags, meta_opcode | (COND_CS << field_shift), \
    949       meta_mask, insn_type, encoding, args },				\
    950   { mnemonic "LO" suffix, flags, meta_opcode | (COND_CS << field_shift), \
    951       meta_mask, insn_type, encoding, args },				\
    952   { mnemonic "CC" suffix, flags, meta_opcode | (COND_CC << field_shift), \
    953       meta_mask, insn_type, encoding, args },				\
    954   { mnemonic "HS" suffix, flags, meta_opcode | (COND_CC << field_shift), \
    955       meta_mask, insn_type, encoding, args },				\
    956   { mnemonic "MI" suffix, flags, meta_opcode | (COND_MI << field_shift), \
    957       meta_mask, insn_type, encoding, args },				\
    958   { mnemonic "N" suffix, flags, meta_opcode | (COND_MI << field_shift),	\
    959       meta_mask, insn_type, encoding, args },				\
    960   { mnemonic "PL" suffix, flags, meta_opcode | (COND_PL << field_shift), \
    961       meta_mask, insn_type, encoding, args },				\
    962   { mnemonic "NC" suffix, flags, meta_opcode | (COND_PL << field_shift), \
    963       meta_mask, insn_type, encoding, args },				\
    964   { mnemonic "VS" suffix, flags, meta_opcode | (COND_VS << field_shift), \
    965       meta_mask, insn_type, encoding, args },				\
    966   { mnemonic "VC" suffix, flags, meta_opcode | (COND_VC << field_shift), \
    967       meta_mask, insn_type, encoding, args },				\
    968   { mnemonic "HI" suffix, flags, meta_opcode | (COND_HI << field_shift), \
    969       meta_mask, insn_type, encoding, args },				\
    970   { mnemonic "LS" suffix, flags, meta_opcode | (COND_LS << field_shift), \
    971       meta_mask, insn_type, encoding, args },				\
    972   { mnemonic "GE" suffix, flags, meta_opcode | (COND_GE << field_shift), \
    973       meta_mask, insn_type, encoding, args },				\
    974   { mnemonic "LT" suffix, flags, meta_opcode | (COND_LT << field_shift), \
    975       meta_mask, insn_type, encoding, args },				\
    976   { mnemonic "GT" suffix, flags, meta_opcode | (COND_GT << field_shift), \
    977       meta_mask, insn_type, encoding, args },				\
    978   { mnemonic "LE" suffix, flags, meta_opcode | (COND_LE << field_shift), \
    979       meta_mask, insn_type, encoding, args },				\
    980   { mnemonic "NV" suffix, flags, meta_opcode | (COND_NV << field_shift), \
    981       meta_mask, insn_type, encoding, args }
    982 
    983 #define TEMPLATE_INSN(flags, meta_opcode, meta_mask, insn_type)		\
    984   { "T0", flags, meta_opcode | 0x0, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
    985   { "T1", flags, meta_opcode | 0x1, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
    986   { "T2", flags, meta_opcode | 0x2, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
    987   { "T3", flags, meta_opcode | 0x3, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
    988   { "T4", flags, meta_opcode | 0x4, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
    989   { "T5", flags, meta_opcode | 0x5, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
    990   { "T6", flags, meta_opcode | 0x6, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
    991   { "T7", flags, meta_opcode | 0x7, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
    992   { "T8", flags, meta_opcode | 0x8, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
    993   { "T9", flags, meta_opcode | 0x9, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
    994   { "TA", flags, meta_opcode | 0xa, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
    995   { "TB", flags, meta_opcode | 0xb, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
    996   { "TC", flags, meta_opcode | 0xc, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
    997   { "TD", flags, meta_opcode | 0xd, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
    998   { "TE", flags, meta_opcode | 0xe, meta_mask, insn_type, ENC_DTEMPLATE, 0 }, \
    999   { "TF", flags, meta_opcode | 0xf, meta_mask, insn_type, ENC_DTEMPLATE, 0 }
   1000 
   1001 
   1002 /* Unimplemented GP instructions:
   1003      CPR - coprocessor read
   1004      CPW - coprocessor write
   1005      MORT - morton order operation
   1006      VPACK, VADD, VSUB - vector instructions
   1007 
   1008    The order of the entries in this table is extremely important. DO
   1009    NOT modify it unless you know what you're doing. If you do modify
   1010    it, be sure to run the entire testsuite to make sure you haven't
   1011    caused a regression.  */
   1012 
   1013 static const insn_template metag_optab[] =
   1014   {
   1015     /* Port-to-unit MOV */
   1016     COND_INSN ("MOVB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1017 	       0xa1800000, 0xfff83e1f, INSN_GP, ENC_MOV_PORT, 0),
   1018     COND_INSN ("MOVW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1019 	       0xa1800001, 0xfff83e1f, INSN_GP, ENC_MOV_PORT, 0),
   1020     COND_INSN ("MOVD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1021 	       0xa1800200, 0xfff83e1f, INSN_GP, ENC_MOV_PORT, 0),
   1022     COND_INSN ("MOVL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1023 	       0xa2800000, 0xfff8019f, INSN_GP, ENC_MOV_PORT, 0),
   1024 
   1025     /* Read pipeline prime/drain */
   1026     { "MMOVD", CoreMeta11|CoreMeta12|CoreMeta21,
   1027       0xca000000, 0xff00001f, INSN_GP, ENC_MMOV, 0 },
   1028     { "MMOVL", CoreMeta11|CoreMeta12|CoreMeta21,
   1029       0xcb000000, 0xff00001f, INSN_GP, ENC_MMOV, 0 },
   1030     { "MMOVD", CoreMeta11|CoreMeta12|CoreMeta21,
   1031       0xcc000000, 0xff07c067, INSN_GP, ENC_MMOV, 0 },
   1032     { "MMOVL", CoreMeta11|CoreMeta12|CoreMeta21,
   1033       0xcd000000, 0xff07c067, INSN_GP, ENC_MMOV, 0 },
   1034 
   1035     /* Read pipeline flush */
   1036     { "MDRD", CoreMeta11|CoreMeta12|CoreMeta21,
   1037       0xcc000002, 0xffffc07f, INSN_GP, ENC_MDRD, 0 },
   1038 
   1039     /* Unit-to-TTREC MOVL */
   1040     COND_INSN ("MOVL", "", 1, CoreMeta12|CoreMeta21,
   1041 	       0xa2002001, 0xff003e7f, INSN_GP, ENC_MOVL_TTREC, 0),
   1042 
   1043     /* MOV to RA (extended) */
   1044     { "MOVB", CoreMeta11|CoreMeta12|CoreMeta21,
   1045       0xa6000000, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 },
   1046     { "MOVW", CoreMeta11|CoreMeta12|CoreMeta21,
   1047       0xa6000002, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 },
   1048     { "MOVD", CoreMeta11|CoreMeta12|CoreMeta21,
   1049       0xa6000004, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 },
   1050     { "MOVL", CoreMeta11|CoreMeta12|CoreMeta21,
   1051       0xa6000006, 0xff00001e, INSN_GP, ENC_GET_SET_EXT, 0 },
   1052 
   1053     /* Extended GET */
   1054     { "GETB", CoreMeta11|CoreMeta12|CoreMeta21,
   1055       0xa7000000, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
   1056     { "GETW", CoreMeta11|CoreMeta12|CoreMeta21,
   1057       0xa7000002, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
   1058     { "GETD", CoreMeta11|CoreMeta12|CoreMeta21,
   1059       0xa7000004, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
   1060     { "GETL", CoreMeta11|CoreMeta12|CoreMeta21,
   1061       0xa7000006, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
   1062 
   1063     /* Extended SET */
   1064     { "SETB", CoreMeta11|CoreMeta12|CoreMeta21,
   1065       0xa5000000, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
   1066     { "SETW", CoreMeta11|CoreMeta12|CoreMeta21,
   1067       0xa5000002, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
   1068     { "SETD", CoreMeta11|CoreMeta12|CoreMeta21,
   1069       0xa5000004, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
   1070     { "SETL", CoreMeta11|CoreMeta12|CoreMeta21,
   1071       0xa5000006, 0xff000006, INSN_GP, ENC_GET_SET_EXT, 0 },
   1072 
   1073     /* MOV to RA */
   1074     { "MOVB", CoreMeta11|CoreMeta12|CoreMeta21,
   1075       0xc000000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 },
   1076     { "MOVW", CoreMeta11|CoreMeta12|CoreMeta21,
   1077       0xc100000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 },
   1078     { "MOVD", CoreMeta11|CoreMeta12|CoreMeta21,
   1079       0xc400000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 },
   1080     { "MOVL", CoreMeta11|CoreMeta12|CoreMeta21,
   1081       0xc500000c, 0xfd00001e, INSN_GP, ENC_GET_SET, 0 },
   1082 
   1083     /* Standard GET */
   1084     { "GETB", CoreMeta11|CoreMeta12|CoreMeta21,
   1085       0xc0000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
   1086     { "GETW", CoreMeta11|CoreMeta12|CoreMeta21,
   1087       0xc1000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
   1088     { "GETD", CoreMeta11|CoreMeta12|CoreMeta21,
   1089       0xc4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
   1090     /* GET is a synonym for GETD. */
   1091     { "GET", CoreMeta11|CoreMeta12|CoreMeta21,
   1092       0xc4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
   1093     { "GETL", CoreMeta11|CoreMeta12|CoreMeta21,
   1094       0xc5000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
   1095 
   1096     /* Standard SET */
   1097     { "SETB", CoreMeta11|CoreMeta12|CoreMeta21,
   1098       0xb0000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
   1099     { "SETW", CoreMeta11|CoreMeta12|CoreMeta21,
   1100       0xb1000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
   1101     { "SETD", CoreMeta11|CoreMeta12|CoreMeta21,
   1102       0xb4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
   1103     /* SET is a synonym for SETD. */
   1104     { "SET", CoreMeta11|CoreMeta12|CoreMeta21,
   1105       0xb4000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
   1106     { "SETL", CoreMeta11|CoreMeta12|CoreMeta21,
   1107       0xb5000000, 0xfd000000, INSN_GP, ENC_GET_SET, 0 },
   1108 
   1109     /* Multiple GET */
   1110     { "MGETD", CoreMeta11|CoreMeta12|CoreMeta21,
   1111       0xc8000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 },
   1112     { "MGETL", CoreMeta11|CoreMeta12|CoreMeta21,
   1113       0xc9000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 },
   1114 
   1115     /* Multiple SET */
   1116     { "MSETD", CoreMeta11|CoreMeta12|CoreMeta21,
   1117       0xb8000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 },
   1118     { "MSETL", CoreMeta11|CoreMeta12|CoreMeta21,
   1119       0xb9000000, 0xff000007, INSN_GP, ENC_MGET_MSET, 0 },
   1120 
   1121     /* Conditional SET */
   1122     COND_INSN ("SETB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1123 	       0xa4000000, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
   1124     COND_INSN ("SETW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1125 	       0xa4000001, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
   1126     COND_INSN ("SETD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1127 	       0xa4000200, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
   1128     COND_INSN ("SETL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1129 	       0xa4000201, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
   1130     { "XFRD", CoreMeta11|CoreMeta12|CoreMeta21,
   1131       0xd0000000, 0xf2000000, INSN_GP, ENC_XFR, 0 },
   1132     { "XFRL", CoreMeta11|CoreMeta12|CoreMeta21,
   1133       0xd2000000, 0xf2000000, INSN_GP, ENC_XFR, 0 },
   1134 
   1135     /* Fast control register setup */
   1136     { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
   1137       0xa9000000, 0xff000005, INSN_GP, ENC_MOV_CT, 0 },
   1138     { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21,
   1139       0xa9000001, 0xff000005, INSN_GP, ENC_MOV_CT, 0 },
   1140     { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
   1141       0xa9000004, 0xff000005, INSN_GP, ENC_MOV_CT, 0 },
   1142     { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21,
   1143       0xa9000005, 0xff000005, INSN_GP, ENC_MOV_CT, 0 },
   1144 
   1145     /* Internal transfer operations */
   1146     { "JUMP", CoreMeta11|CoreMeta12|CoreMeta21,
   1147       0xac000000, 0xff000004, INSN_GP, ENC_JUMP, 0 },
   1148     { "CALL", CoreMeta11|CoreMeta12|CoreMeta21,
   1149       0xac000004, 0xff000004, INSN_GP, ENC_JUMP, 0 },
   1150     { "CALLR", CoreMeta11|CoreMeta12|CoreMeta21,
   1151       0xab000000, 0xff000000, INSN_GP, ENC_CALLR, 0 },
   1152 
   1153     /* Address unit ALU operations */
   1154     { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
   1155       0x80000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
   1156     { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
   1157       0x82000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1158     { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21,
   1159       0x82000005, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1160     { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
   1161       0x80000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
   1162     { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
   1163       0x82000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1164     { "ADDT", CoreMeta11|CoreMeta12|CoreMeta21,
   1165       0x82000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1166     { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
   1167       0x86000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
   1168     COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1169 	       0x84000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
   1170     COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1171 	       0x86000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
   1172     { "NEG", CoreMeta11|CoreMeta12|CoreMeta21,
   1173       0x88000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
   1174     { "NEG", CoreMeta11|CoreMeta12|CoreMeta21,
   1175       0x8a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1176     { "NEGT", CoreMeta11|CoreMeta12|CoreMeta21,
   1177       0x8a000005, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1178     { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
   1179       0x88000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
   1180     { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
   1181       0x8a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1182     { "SUBT", CoreMeta11|CoreMeta12|CoreMeta21,
   1183       0x8a000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1184     { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
   1185       0x8e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
   1186     COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1187 	       0x8c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
   1188     COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1189 	       0x8e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
   1190 
   1191     /* Data unit ALU operations */
   1192     { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
   1193       0x00000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
   1194     { "MOVS", CoreMeta11|CoreMeta12|CoreMeta21,
   1195       0x08000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
   1196     { "MOV", CoreMeta11|CoreMeta12|CoreMeta21,
   1197       0x02000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1198     { "MOVS", CoreMeta11|CoreMeta12|CoreMeta21,
   1199       0x0a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1200     { "MOVT", CoreMeta11|CoreMeta12|CoreMeta21,
   1201       0x02000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
   1202     { "MOVST", CoreMeta11|CoreMeta12|CoreMeta21,
   1203       0x0a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
   1204     { "ADD", DspMeta21,
   1205       0x00000100, 0xfe000104, INSN_DSP, ENC_DALU,
   1206       DSP_ARGS_1|DSP_ARGS_ACC2|DSP_ARGS_XACC|DSP_ARGS_IMM },
   1207     { "ADD", DspMeta21,
   1208       0x02000003, 0xfe000003, INSN_DSP, ENC_DALU,
   1209       DSP_ARGS_1|DSP_ARGS_IMM },
   1210     COND_INSN ("ADD", "", 1, DspMeta21,
   1211 	       0x040001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1),
   1212     { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
   1213       0x00000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
   1214     { "ADDS", DspMeta21,
   1215       0x08000100, 0xfe000104, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_ACC2 },
   1216     { "ADDS", DspMeta21,
   1217       0x0a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
   1218     { "ADDS", CoreMeta11|CoreMeta12|CoreMeta21,
   1219       0x08000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
   1220     { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
   1221       0x02000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1222     { "ADDS", CoreMeta11|CoreMeta12|CoreMeta21,
   1223       0x0a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1224     { "ADDT", CoreMeta11|CoreMeta12|CoreMeta21,
   1225       0x02000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1226     { "ADDST", CoreMeta11|CoreMeta12|CoreMeta21,
   1227       0x0a000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1228     { "ADD", CoreMeta11|CoreMeta12|CoreMeta21,
   1229       0x06000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
   1230     COND_INSN ("ADDS", "", 1, DspMeta21,
   1231 	       0x0c0001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1),
   1232     { "ADDS", CoreMeta11|CoreMeta12|CoreMeta21,
   1233       0x0e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
   1234     COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1235 	       0x04000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
   1236     COND_INSN ("ADDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1237 	       0x0c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
   1238     COND_INSN ("ADD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1239 	       0x06000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
   1240     COND_INSN ("ADDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1241 	       0x0e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
   1242     { "NEG", CoreMeta11|CoreMeta12|CoreMeta21,
   1243       0x10000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
   1244     { "NEGS", CoreMeta11|CoreMeta12|CoreMeta21,
   1245       0x18000004, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
   1246     { "NEG", CoreMeta11|CoreMeta12|CoreMeta21,
   1247       0x12000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1248     { "NEGS", CoreMeta11|CoreMeta12|CoreMeta21,
   1249       0x1a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1250     { "NEGT", CoreMeta11|CoreMeta12|CoreMeta21,
   1251       0x12000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
   1252     { "NEGST", CoreMeta11|CoreMeta12|CoreMeta21,
   1253       0x1a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
   1254     { "SUB", DspMeta21,
   1255       0x10000100, 0xfe000104, INSN_DSP, ENC_DALU,
   1256       DSP_ARGS_1|DSP_ARGS_ACC2|DSP_ARGS_XACC },
   1257     { "SUB", DspMeta21,
   1258       0x12000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
   1259     { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
   1260       0x10000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
   1261     { "SUBS", CoreMeta11|CoreMeta12|CoreMeta21,
   1262       0x18000000, 0xfe0001fc, INSN_GP, ENC_ALU, 0 },
   1263     { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
   1264       0x12000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1265     { "SUBS", CoreMeta11|CoreMeta12|CoreMeta21,
   1266       0x1a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1267     { "SUBT", CoreMeta11|CoreMeta12|CoreMeta21,
   1268       0x12000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1269     { "SUBS", DspMeta21,
   1270       0x18000100, 0xfe000104, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_ACC2 },
   1271     { "SUBS", DspMeta21,
   1272       0x1a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
   1273     { "SUBST", CoreMeta11|CoreMeta12|CoreMeta21,
   1274       0x1a000001, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1275     { "SUB", CoreMeta11|CoreMeta12|CoreMeta21,
   1276       0x16000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
   1277     { "SUBS", CoreMeta11|CoreMeta12|CoreMeta21,
   1278       0x1e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
   1279     COND_INSN ("SUBS", "", 1, DspMeta21,
   1280 	       0x1c0001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1),
   1281     COND_INSN ("SUB", "", 1, DspMeta21,
   1282 	       0x140001e0, 0xfe0001fe, INSN_DSP, ENC_DALU, DSP_ARGS_1),
   1283     COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1284 	       0x14000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
   1285     COND_INSN ("SUBS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1286 	       0x1c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
   1287     COND_INSN ("SUB", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1288 	       0x16000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
   1289     COND_INSN ("SUBS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1290 	       0x1e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
   1291     { "AND", CoreMeta11|CoreMeta12|CoreMeta21,
   1292       0x20000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
   1293     { "ANDS", CoreMeta11|CoreMeta12|CoreMeta21,
   1294       0x28000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
   1295     { "ANDQ", CoreMeta11|CoreMeta12|CoreMeta21,
   1296       0x20000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
   1297     { "ANDSQ", CoreMeta11|CoreMeta12|CoreMeta21,
   1298       0x28000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
   1299     { "AND", CoreMeta11|CoreMeta12|CoreMeta21,
   1300       0x22000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1301     { "ANDMB", CoreMeta11|CoreMeta12|CoreMeta21,
   1302       0x22000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1303     { "ANDS", CoreMeta11|CoreMeta12|CoreMeta21,
   1304       0x2a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1305     { "ANDSMB", CoreMeta11|CoreMeta12|CoreMeta21,
   1306       0x2a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1307     { "ANDT", CoreMeta11|CoreMeta12|CoreMeta21,
   1308       0x22000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
   1309     { "ANDMT", CoreMeta11|CoreMeta12|CoreMeta21,
   1310       0x22000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
   1311     { "ANDST", CoreMeta11|CoreMeta12|CoreMeta21,
   1312       0x2a000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
   1313     { "ANDSMT", CoreMeta11|CoreMeta12|CoreMeta21,
   1314       0x2a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
   1315     { "AND", DspMeta21,
   1316       0x20000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
   1317     { "AND", CoreMeta11|CoreMeta12|CoreMeta21,
   1318       0x26000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
   1319     { "ANDS", CoreMeta11|CoreMeta12|CoreMeta21,
   1320       0x2e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
   1321     { "ANDQ", CoreMeta11|CoreMeta12|CoreMeta21,
   1322       0x26000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
   1323     { "ANDSQ", CoreMeta11|CoreMeta12|CoreMeta21,
   1324       0x2e000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
   1325     { "ANDQ", DspMeta21,
   1326       0x20000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
   1327     COND_INSN ("ANDQ", "", 1, DspMeta21,
   1328 	       0x240001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
   1329 	       DSP_ARGS_1|DSP_ARGS_QR),
   1330     COND_INSN ("AND", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1331 	       0x24000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
   1332     { "ANDSQ", DspMeta21,
   1333       0x28000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
   1334     COND_INSN ("ANDSQ", "", 1, DspMeta21,
   1335 	       0x2c0001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
   1336 	       DSP_ARGS_1|DSP_ARGS_QR),
   1337     COND_INSN ("ANDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1338 	       0x2c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
   1339     COND_INSN ("AND", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1340 	       0x26000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
   1341     COND_INSN ("ANDS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1342 	       0x2e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
   1343     COND_INSN ("ANDQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1344 	       0x26000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
   1345     COND_INSN ("ANDSQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1346 	       0x2e000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
   1347     { "OR", CoreMeta11|CoreMeta12|CoreMeta21,
   1348       0x30000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
   1349     { "ORS", CoreMeta11|CoreMeta12|CoreMeta21,
   1350       0x38000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
   1351     { "ORQ", CoreMeta11|CoreMeta12|CoreMeta21,
   1352       0x30000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
   1353     { "ORSQ", CoreMeta11|CoreMeta12|CoreMeta21,
   1354       0x38000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
   1355     { "OR", CoreMeta11|CoreMeta12|CoreMeta21,
   1356       0x32000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1357     { "ORMB", CoreMeta11|CoreMeta12|CoreMeta21,
   1358       0x32000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1359     { "ORS", CoreMeta11|CoreMeta12|CoreMeta21,
   1360       0x3a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1361     { "ORSMB", CoreMeta11|CoreMeta12|CoreMeta21,
   1362       0x3a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1363     { "ORT", CoreMeta11|CoreMeta12|CoreMeta21,
   1364       0x32000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
   1365     { "ORMT", CoreMeta11|CoreMeta12|CoreMeta21,
   1366       0x32000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
   1367     { "ORST", CoreMeta11|CoreMeta12|CoreMeta21,
   1368       0x3a000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
   1369     { "ORSMT", CoreMeta11|CoreMeta12|CoreMeta21,
   1370       0x3a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
   1371     { "OR", CoreMeta11|CoreMeta12|CoreMeta21,
   1372       0x36000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
   1373     { "ORS", CoreMeta11|CoreMeta12|CoreMeta21,
   1374       0x3e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
   1375     { "ORQ", CoreMeta11|CoreMeta12|CoreMeta21,
   1376       0x36000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
   1377     { "ORSQ", CoreMeta11|CoreMeta12|CoreMeta21,
   1378       0x3e000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
   1379     { "ORQ", DspMeta21,
   1380       0x30000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
   1381     COND_INSN ("ORQ", "", 1, DspMeta21,
   1382 	       0x340001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
   1383 	       DSP_ARGS_1|DSP_ARGS_QR),
   1384     COND_INSN ("OR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1385 	       0x34000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
   1386     { "ORSQ", DspMeta21,
   1387       0x38000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
   1388     COND_INSN ("ORSQ", "", 1, DspMeta21,
   1389 	       0x3c0001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
   1390 	       DSP_ARGS_1|DSP_ARGS_QR),
   1391     COND_INSN ("ORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1392 	       0x3c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
   1393     COND_INSN ("OR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1394 	       0x36000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
   1395     COND_INSN ("ORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1396 	       0x3e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
   1397     COND_INSN ("ORQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1398 	       0x36000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
   1399     COND_INSN ("ORSQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1400 	       0x3e000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
   1401     { "XOR", CoreMeta11|CoreMeta12|CoreMeta21,
   1402       0x40000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
   1403     { "XORS", CoreMeta11|CoreMeta12|CoreMeta21,
   1404       0x48000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
   1405     { "XORQ", CoreMeta11|CoreMeta12|CoreMeta21,
   1406       0x40000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
   1407     { "XORSQ", CoreMeta11|CoreMeta12|CoreMeta21,
   1408       0x48000040, 0xfe00017e, INSN_GP, ENC_ALU, GP_ARGS_QR },
   1409     { "XOR", CoreMeta11|CoreMeta12|CoreMeta21,
   1410       0x42000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1411     { "XORMB", CoreMeta11|CoreMeta12|CoreMeta21,
   1412       0x42000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1413     { "XORS", CoreMeta11|CoreMeta12|CoreMeta21,
   1414       0x4a000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1415     { "XORSMB", CoreMeta11|CoreMeta12|CoreMeta21,
   1416       0x4a000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1417     { "XORT", CoreMeta11|CoreMeta12|CoreMeta21,
   1418       0x42000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
   1419     { "XORMT", CoreMeta11|CoreMeta12|CoreMeta21,
   1420       0x42000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
   1421     { "XORST", CoreMeta11|CoreMeta12|CoreMeta21,
   1422       0x4a000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
   1423     { "XORSMT", CoreMeta11|CoreMeta12|CoreMeta21,
   1424       0x4a000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
   1425     { "XOR", CoreMeta11|CoreMeta12|CoreMeta21,
   1426       0x46000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
   1427     { "XORS", CoreMeta11|CoreMeta12|CoreMeta21,
   1428       0x4e000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
   1429     { "XORQ", CoreMeta11|CoreMeta12|CoreMeta21,
   1430       0x46000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
   1431     { "XORSQ", CoreMeta11|CoreMeta12|CoreMeta21,
   1432       0x4e000021, 0xfe000021, INSN_GP, ENC_ALU, GP_ARGS_QR },
   1433     { "XORQ", DspMeta21,
   1434       0x40000140, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
   1435     COND_INSN ("XORQ", "", 1, DspMeta21,
   1436 	       0x440001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
   1437 	       DSP_ARGS_1|DSP_ARGS_QR),
   1438     COND_INSN ("XOR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1439 	       0x44000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
   1440     { "XORSQ", DspMeta21,
   1441       0x48000140, 0xfe000140, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_QR },
   1442     COND_INSN ("XORSQ", "", 1, DspMeta21,
   1443 	       0x4c0001c0, 0xfe0001de, INSN_DSP, ENC_DALU,
   1444 	       DSP_ARGS_1|DSP_ARGS_QR),
   1445     COND_INSN ("XORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1446 	       0x4c000000, 0xfe00001e, INSN_GP, ENC_ALU, 0),
   1447     COND_INSN ("XOR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1448 	       0x46000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
   1449     COND_INSN ("XORS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1450 	       0x4e000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
   1451     COND_INSN ("XORQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1452 	       0x46000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
   1453     COND_INSN ("XORSQ", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1454 	       0x4e000001, 0xfe00003f, INSN_GP, ENC_ALU, GP_ARGS_QR),
   1455     { "LSL", CoreMeta11|CoreMeta12|CoreMeta21,
   1456       0x50000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
   1457     { "LSL", CoreMeta11|CoreMeta12|CoreMeta21,
   1458       0x54000020, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
   1459     COND_INSN ("LSL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1460 	       0x54000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
   1461     { "LSLS", CoreMeta11|CoreMeta12|CoreMeta21,
   1462       0x58000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
   1463     { "LSLS", CoreMeta11|CoreMeta12|CoreMeta21,
   1464       0x5c000020, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
   1465     COND_INSN ("LSLS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1466 	       0x5c000000, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
   1467     { "LSR", CoreMeta11|CoreMeta12|CoreMeta21,
   1468       0x50000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
   1469     { "LSR", CoreMeta11|CoreMeta12|CoreMeta21,
   1470       0x54000060, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
   1471     COND_INSN ("LSR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1472 	       0x54000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
   1473     { "LSRS", CoreMeta11|CoreMeta12|CoreMeta21,
   1474       0x58000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
   1475     { "LSRS", CoreMeta11|CoreMeta12|CoreMeta21,
   1476       0x5c000060, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
   1477     COND_INSN ("LSRS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1478 	       0x5c000040, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
   1479     { "ASL", CoreMeta11|CoreMeta12|CoreMeta21,
   1480       0x50000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
   1481     { "ASL", CoreMeta11|CoreMeta12|CoreMeta21,
   1482       0x540000a0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
   1483     COND_INSN ("ASL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1484 	       0x54000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
   1485     { "ASLS", CoreMeta11|CoreMeta12|CoreMeta21,
   1486       0x58000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
   1487     { "ASLS", CoreMeta11|CoreMeta12|CoreMeta21,
   1488       0x5c0000a0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
   1489     COND_INSN ("ASLS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1490 	       0x5c000080, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
   1491     { "ASR", CoreMeta11|CoreMeta12|CoreMeta21,
   1492       0x500000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
   1493     { "ASR", CoreMeta11|CoreMeta12|CoreMeta21,
   1494       0x540000e0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
   1495     COND_INSN ("ASR", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1496 	       0x540000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
   1497     { "ASRS", CoreMeta11|CoreMeta12|CoreMeta21,
   1498       0x580000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0 },
   1499     { "ASRS", CoreMeta11|CoreMeta12|CoreMeta21,
   1500       0x5c0000e0, 0xfc0001e0, INSN_GP, ENC_SHIFT, 0 },
   1501     COND_INSN ("ASRS", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1502 	       0x5c0000c0, 0xfc0001ff, INSN_GP, ENC_SHIFT, 0),
   1503     { "MULW", CoreMeta11|CoreMeta12|CoreMeta21,
   1504       0x60000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
   1505     { "MULD", CoreMeta11|CoreMeta12|CoreMeta21,
   1506       0x60000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
   1507     /* MUL is a synonym from MULD. */
   1508     { "MUL", CoreMeta11|CoreMeta12|CoreMeta21,
   1509       0x60000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0 },
   1510     { "MULW", CoreMeta11|CoreMeta12|CoreMeta21,
   1511       0x62000000, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1512     { "MULD", CoreMeta11|CoreMeta12|CoreMeta21,
   1513       0x62000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1514     { "MUL", CoreMeta11|CoreMeta12|CoreMeta21,
   1515       0x62000004, 0xfe000005, INSN_GP, ENC_ALU, 0 },
   1516     { "MULWT", CoreMeta11|CoreMeta12|CoreMeta21,
   1517       0x62000001, 0xfe000007, INSN_GP, ENC_ALU, 0 },
   1518     { "MULDT", CoreMeta11|CoreMeta12|CoreMeta21,
   1519       0x62000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
   1520     { "MULT", CoreMeta11|CoreMeta12|CoreMeta21,
   1521       0x62000005, 0xfe000007, INSN_GP, ENC_ALU, 0 },
   1522     { "MULW", CoreMeta11|CoreMeta12|CoreMeta21,
   1523       0x64000020, 0xfe0001e0, INSN_GP, ENC_ALU, 0 },
   1524     { "MULD", CoreMeta11|CoreMeta12|CoreMeta21,
   1525       0x64000060, 0xfe0001e0, INSN_GP, ENC_ALU, 0 },
   1526     { "MUL", CoreMeta11|CoreMeta12|CoreMeta21,
   1527       0x64000060, 0xfe0001e0, INSN_GP, ENC_ALU, 0 },
   1528     { "MULW", CoreMeta11|CoreMeta12|CoreMeta21,
   1529       0x66000020, 0xfe000021, INSN_GP, ENC_ALU, 0 },
   1530     { "MULD", CoreMeta11|CoreMeta12|CoreMeta21,
   1531       0x66000021, 0xfe000021, INSN_GP, ENC_ALU, 0 },
   1532     { "MUL", CoreMeta11|CoreMeta12|CoreMeta21,
   1533       0x66000021, 0xfe000021, INSN_GP, ENC_ALU, 0 },
   1534     COND_INSN ("MULW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1535 	       0x64000000, 0xfe0001fe, INSN_GP, ENC_ALU, 0),
   1536     COND_INSN ("MULD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1537 	       0x64000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0),
   1538     COND_INSN ("MUL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1539 	       0x64000040, 0xfe0001fe, INSN_GP, ENC_ALU, 0),
   1540     COND_INSN ("MULW", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1541 	       0x66000000, 0xfe00003f, INSN_GP, ENC_ALU, 0),
   1542     COND_INSN ("MULD", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1543 	       0x66000001, 0xfe00003f, INSN_GP, ENC_ALU, 0),
   1544     COND_INSN ("MUL", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1545 	       0x66000001, 0xfe00003f, INSN_GP, ENC_ALU, 0),
   1546     { "MIN", CoreMeta11|CoreMeta12|CoreMeta21,
   1547       0x70000020, 0xfe0001ff, INSN_GP, ENC_MIN_MAX, 0 },
   1548     { "MAX", CoreMeta11|CoreMeta12|CoreMeta21,
   1549       0x70000024, 0xfe0001ff, INSN_GP, ENC_MIN_MAX, 0 },
   1550     { "FFB", CoreMeta11|CoreMeta12|CoreMeta21,
   1551       0x70000004, 0xfe003fff, INSN_GP, ENC_BITOP, 0 },
   1552     { "NORM", CoreMeta11|CoreMeta12|CoreMeta21,
   1553       0x70000008, 0xfe003fff, INSN_GP, ENC_BITOP, 0 },
   1554     { "ABS", CoreMeta11|CoreMeta12|CoreMeta21,
   1555       0x70000028, 0xfe003fff, INSN_GP, ENC_BITOP, 0 },
   1556     { "XSDB", CoreMeta11|CoreMeta12|CoreMeta21,
   1557       0xaa000000, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
   1558     { "XSDSB", CoreMeta11|CoreMeta12|CoreMeta21,
   1559       0xaa000008, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
   1560     { "XSDW", CoreMeta11|CoreMeta12|CoreMeta21,
   1561       0xaa000002, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
   1562     { "XSDSW", CoreMeta11|CoreMeta12|CoreMeta21,
   1563       0xaa00000a, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
   1564     { "RTDW", CoreMeta11|CoreMeta12|CoreMeta21,
   1565       0xaa000006, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
   1566     { "RTDSW", CoreMeta11|CoreMeta12|CoreMeta21,
   1567       0xaa00000e, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
   1568     { "NMIN", CoreMeta11|CoreMeta12|CoreMeta21,
   1569       0x7000002c, 0xfe0001ff, INSN_GP, ENC_MIN_MAX, 0 },
   1570 
   1571     /* Condition setting operations */
   1572     { "CMP", CoreMeta11|CoreMeta12|CoreMeta21,
   1573       0x70000000, 0xfef801fe, INSN_GP, ENC_CMP, 0 },
   1574     { "TST", CoreMeta11|CoreMeta12|CoreMeta21,
   1575       0x78000000, 0xfef801fe, INSN_GP, ENC_CMP, 0 },
   1576     { "CMP", CoreMeta11|CoreMeta12|CoreMeta21,
   1577       0x72000000, 0xfe000005, INSN_GP, ENC_CMP, 0 },
   1578     { "CMPMB", CoreMeta11|CoreMeta12|CoreMeta21,
   1579       0x72000004, 0xfe000005, INSN_GP, ENC_CMP, 0 },
   1580     { "TST", CoreMeta11|CoreMeta12|CoreMeta21,
   1581       0x7a000000, 0xfe000005, INSN_GP, ENC_CMP, 0 },
   1582     { "TSTMB", CoreMeta11|CoreMeta12|CoreMeta21,
   1583       0x7a000004, 0xfe000005, INSN_GP, ENC_CMP, 0 },
   1584     { "CMPT", CoreMeta11|CoreMeta12|CoreMeta21,
   1585       0x72000001, 0xfe000007, INSN_GP, ENC_CMP, 0 },
   1586     { "CMPMT", CoreMeta11|CoreMeta12|CoreMeta21,
   1587       0x72000005, 0xfe000007, INSN_GP, ENC_CMP, 0 },
   1588     { "TSTT", CoreMeta11|CoreMeta12|CoreMeta21,
   1589       0x7a000001, 0xfe000007, INSN_GP, ENC_CMP, 0 },
   1590     { "TSTMT", CoreMeta11|CoreMeta12|CoreMeta21,
   1591       0x7a000005, 0xfe000007, INSN_GP, ENC_CMP, 0 },
   1592     COND_INSN ("CMP", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1593 	       0x74000000, 0xfef801fe, INSN_GP, ENC_CMP, 0),
   1594     COND_INSN ("TST", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1595 	       0x7c000000, 0xfef801fe, INSN_GP, ENC_CMP, 0),
   1596     COND_INSN ("CMP", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1597 	       0x76000000, 0xfef8003e, INSN_GP, ENC_CMP, 0),
   1598     COND_INSN ("TST", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1599 	       0x7e000000, 0xfef8003e, INSN_GP, ENC_CMP, 0),
   1600 
   1601     /* No-op (BNV) */
   1602     { "NOP", CoreMeta11|CoreMeta12|CoreMeta21,
   1603       0xa0fffffe, 0xffffffff, INSN_GP, ENC_NONE, 0 },
   1604 
   1605     /* Branch */
   1606     COND_INSN ("B", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1607 	       0xa0000000, 0xff00001f, INSN_GP, ENC_BRANCH, 0),
   1608     COND_INSN ("B", "R", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1609 	       0xa0000001, 0xff00001f, INSN_GP, ENC_BRANCH, 0),
   1610 
   1611     /* System operations */
   1612     { "LOCK0", CoreMeta11|CoreMeta12|CoreMeta21,
   1613       0xa8000000, 0xffffffff, INSN_GP, ENC_NONE, 0 },
   1614     { "LOCK1", CoreMeta11|CoreMeta12|CoreMeta21,
   1615       0xa8000001, 0xffffffff, INSN_GP, ENC_NONE, 0 },
   1616     { "LOCK2", CoreMeta11|CoreMeta12|CoreMeta21,
   1617       0xa8000003, 0xffffffff, INSN_GP, ENC_NONE, 0 },
   1618     { "RTI", CoreMeta11|CoreMeta12|CoreMeta21,
   1619       0xa3ffffff, 0xffffffff, INSN_GP, ENC_NONE, 0 },
   1620     { "RTH", CoreMeta11|CoreMeta12|CoreMeta21,
   1621       0xa37fffff, 0xffffffff, INSN_GP, ENC_NONE, 0 },
   1622     COND_INSN ("KICK", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1623 	       0xa3000001, 0xff003e1f, INSN_GP, ENC_KICK, 0),
   1624     { "SWITCH", CoreMeta11|CoreMeta12|CoreMeta21,
   1625       0xaf000000, 0xff000000, INSN_GP, ENC_SWITCH, 0 },
   1626     { "DCACHE", CoreMeta11|CoreMeta12|CoreMeta21,
   1627       0xad000000, 0xff000087, INSN_GP, ENC_CACHEW, 0 },
   1628     { "ICACHEEXIT", CoreMeta12|CoreMeta21,
   1629       0xae000000, 0xffffffff, INSN_GP, ENC_NONE, 0 },
   1630     { "ICACHEEXITR", CoreMeta12|CoreMeta21,
   1631       0xae000001, 0xffffffff, INSN_GP, ENC_NONE, 0 },
   1632     { "ICACHE", CoreMeta12|CoreMeta21,
   1633       0xae000000, 0xff0001e1, INSN_GP, ENC_ICACHE, 0 },
   1634     { "ICACHER", CoreMeta12|CoreMeta21,
   1635       0xae000001, 0xff0001e1, INSN_GP, ENC_ICACHE, 0 },
   1636 
   1637     /* Meta 2 instructions */
   1638     { "CACHERD", CoreMeta21,
   1639       0xad000081, 0xff000087, INSN_GP, ENC_CACHER, 0 },
   1640     { "CACHERL", CoreMeta21,
   1641       0xad000083, 0xff000087, INSN_GP, ENC_CACHER, 0 },
   1642     { "CACHEWD", CoreMeta21,
   1643       0xad000001, 0xff000087, INSN_GP, ENC_CACHEW, 0 },
   1644     { "CACHEWL", CoreMeta21,
   1645       0xad000003, 0xff000087, INSN_GP, ENC_CACHEW, 0 },
   1646     COND_INSN ("DEFR", "", 1, CoreMeta21,
   1647 	       0xa3002001, 0xff003e1f, INSN_GP, ENC_KICK, 0),
   1648     { "BEXD", CoreMeta21,
   1649       0xaa000004, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
   1650     { "BEXSD", CoreMeta21,
   1651       0xaa00000c, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
   1652     { "BEXL", CoreMeta21,
   1653       0xaa000014, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
   1654     { "BEXSL", CoreMeta21,
   1655       0xaa00001c, 0xff003ffe, INSN_GP, ENC_BITOP, 0 },
   1656     { "LNKGETB", CoreMeta21,
   1657       0xad000080, 0xff000087, INSN_GP, ENC_LNKGET, 0 },
   1658     { "LNKGETW", CoreMeta21,
   1659       0xad000082, 0xff000087, INSN_GP, ENC_LNKGET, 0 },
   1660     { "LNKGETD", CoreMeta21,
   1661       0xad000084, 0xff000087, INSN_GP, ENC_LNKGET, 0 },
   1662     { "LNKGETL", CoreMeta21,
   1663       0xad000086, 0xff000087, INSN_GP, ENC_LNKGET, 0 },
   1664     COND_INSN ("LNKSETB", "", 1, CoreMeta21,
   1665 	       0xa4000080, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
   1666     COND_INSN ("LNKSETW", "", 1, CoreMeta21,
   1667 	       0xa4000081, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
   1668     COND_INSN ("LNKSETD", "", 1, CoreMeta21,
   1669 	       0xa4000280, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
   1670     COND_INSN ("LNKSETL", "", 1, CoreMeta21,
   1671 	       0xa4000281, 0xff00039f, INSN_GP, ENC_COND_SET, 0),
   1672 
   1673     /* Meta 2 FPU instructions */
   1674 
   1675     /* Port-to-unit MOV */
   1676     COND_INSN ("MOVL", "", 1, FpuMeta21,
   1677 	       0xa1800201, 0xfff83e1f, INSN_FPU, ENC_MOV_PORT, 0),
   1678 
   1679     /* Read pipeline drain */
   1680     { "MMOVD", FpuMeta21,
   1681       0xce000006, 0xfffc007f, INSN_FPU, ENC_MMOV, 0 },
   1682     { "MMOVL", FpuMeta21,
   1683       0xcf000006, 0xfffc007f, INSN_FPU, ENC_MMOV, 0 },
   1684 
   1685     /* FP data movement instructions */
   1686     FCOND_INSN ("ABS", "", 1, FpuMeta21,
   1687 		0xf0000080, 0xff843f9f, INSN_FPU, ENC_FMOV, 0),
   1688     { "MMOVD", FpuMeta21,
   1689       0xbe000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
   1690     { "MMOVL", FpuMeta21,
   1691       0xbf000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
   1692     { "MMOVD", FpuMeta21,
   1693       0xce000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
   1694     { "MMOVL", FpuMeta21,
   1695       0xcf000002, 0xff84007e, INSN_FPU, ENC_FMMOV, 0 },
   1696     { "MOVD", FpuMeta21,
   1697       0x08000144, 0xfe03e1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
   1698     { "MOVD", FpuMeta21,
   1699       0x080001c4, 0xfe83c1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
   1700     { "MOVL", FpuMeta21,
   1701       0x08000154, 0xfe03e1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
   1702     { "MOVL", FpuMeta21,
   1703       0x080001d4, 0xfe83c1ff, INSN_FPU, ENC_FMOV_DATA, 0 },
   1704     FCOND_INSN ("MOV", "", 1, FpuMeta21,
   1705 		0xf0000000, 0xff843f9f, INSN_FPU, ENC_FMOV, 0),
   1706     { "MOV", FpuMeta21,
   1707       0xf0000001, 0xff800001, INSN_FPU, ENC_FMOV_I, 0 },
   1708     FCOND_INSN ("NEG", "", 1, FpuMeta21,
   1709 		0xf0000100, 0xff843f9f, INSN_FPU, ENC_FMOV, 0),
   1710     { "PACK", FpuMeta21,
   1711       0xf0000180, 0xff8c21ff, INSN_FPU, ENC_FPACK, 0 },
   1712     { "SWAP", FpuMeta21,
   1713       0xf00001c0, 0xff8c7fff, INSN_FPU, ENC_FSWAP, 0 },
   1714 
   1715     /* FP comparison instructions */
   1716     FCOND_INSN ("CMP", "", 1, FpuMeta21,
   1717 		0xf3000000, 0xfff4201f, INSN_FPU, ENC_FCMP, 0),
   1718     FCOND_INSN ("MAX", "", 1, FpuMeta21,
   1719 		0xf3000081, 0xff84219f, INSN_FPU, ENC_FMINMAX, 0),
   1720     FCOND_INSN ("MIN", "", 1, FpuMeta21,
   1721 		0xf3000001, 0xff84219f, INSN_FPU, ENC_FMINMAX, 0),
   1722 
   1723     /* FP data conversion instructions */
   1724     FCOND_INSN ("DTOF", "", 1, FpuMeta21,
   1725 		0xf2000121, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
   1726     FCOND_INSN ("FTOD", "", 1, FpuMeta21,
   1727 		0xf2000101, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
   1728     FCOND_INSN ("DTOH", "", 1, FpuMeta21,
   1729 		0xf2000320, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
   1730     FCOND_INSN ("FTOH", "", 1, FpuMeta21,
   1731 		0xf2000300, 0xff843fbf, INSN_FPU, ENC_FCONV, 0),
   1732     FCOND_INSN ("DTOI", "", 1, FpuMeta21,
   1733 		0xf2002120, 0xff842fff, INSN_FPU, ENC_FCONV, 0),
   1734     FCOND_INSN ("FTOI", "", 1, FpuMeta21,
   1735 		0xf2002100, 0xff842fbf, INSN_FPU, ENC_FCONV, 0),
   1736     FCOND_INSN ("DTOL", "", 1, FpuMeta21,
   1737 		0xf2002320, 0xff8c6fff, INSN_FPU, ENC_FCONV, 0),
   1738 
   1739     FCOND_INSN ("DTOX", "", 1, FpuMeta21,
   1740 		0xf2000020, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
   1741     FCOND_INSN ("FTOX", "", 1, FpuMeta21,
   1742 		0xf2000000, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
   1743     FCOND_INSN ("DTOXL", "", 1, FpuMeta21,
   1744 		0xf20000a0, 0xff8c40ff, INSN_FPU, ENC_FCONVX, 0),
   1745 
   1746     FCOND_INSN ("HTOD", "", 1, FpuMeta21,
   1747 		0xf2000321, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
   1748     FCOND_INSN ("HTOF", "", 1, FpuMeta21,
   1749 		0xf2000301, 0xff843fbf, INSN_FPU, ENC_FCONV, 0),
   1750     FCOND_INSN ("ITOD", "", 1, FpuMeta21,
   1751 		0xf2002121, 0xff843fff, INSN_FPU, ENC_FCONV, 0),
   1752     FCOND_INSN ("ITOF", "", 1, FpuMeta21,
   1753 		0xf2002101, 0xff843fbf, INSN_FPU, ENC_FCONV, 0),
   1754     FCOND_INSN ("LTOD", "", 1, FpuMeta21,
   1755 		0xf2002321, 0xff8c7fff, INSN_FPU, ENC_FCONV, 0),
   1756 
   1757     FCOND_INSN ("XTOD", "", 1, FpuMeta21,
   1758 		0xf2000021, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
   1759     FCOND_INSN ("XTOF", "", 1, FpuMeta21,
   1760 		0xf2000001, 0xff8401bf, INSN_FPU, ENC_FCONVX, 0),
   1761     FCOND_INSN ("XLTOD", "", 1, FpuMeta21,
   1762 		0xf20000a1, 0xff8c40ff, INSN_FPU, ENC_FCONVX, 0),
   1763 
   1764     /* FP basic arithmetic instructions */
   1765     FCOND_INSN ("ADD", "", 1, FpuMeta21,
   1766 		0xf1000001, 0xff84211f, INSN_FPU, ENC_FBARITH, 0),
   1767     FCOND_INSN ("MUL", "", 1, FpuMeta21,
   1768 		0xf1000100, 0xff84211f, INSN_FPU, ENC_FBARITH, 0),
   1769     FCOND_INSN ("SUB", "", 1, FpuMeta21,
   1770 		0xf1000101, 0xff84211f, INSN_FPU, ENC_FBARITH, 0),
   1771 
   1772     /* FP extended arithmetic instructions */
   1773     { "MAC", FpuMeta21,
   1774       0xf6000000, 0xfffc219f, INSN_FPU, ENC_FEARITH, 0 },
   1775     { "MACS", FpuMeta21,
   1776       0xf6000100, 0xfffc219f, INSN_FPU, ENC_FEARITH, 0 },
   1777 
   1778     { "MAR", FpuMeta21,
   1779       0xf6000004, 0xff84211f, INSN_FPU, ENC_FEARITH, 0 },
   1780     { "MARS", FpuMeta21,
   1781       0xf6000104, 0xff84211f, INSN_FPU, ENC_FEARITH, 0 },
   1782 
   1783     { "MAW", FpuMeta21,
   1784       0xf6000008, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
   1785     { "MAWS", FpuMeta21,
   1786       0xf6000108, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
   1787     { "MAW1", FpuMeta21,
   1788       0xf6000009, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
   1789     { "MAWS1", FpuMeta21,
   1790       0xf6000109, 0xff84219f, INSN_FPU, ENC_FEARITH, 0 },
   1791 
   1792     FCOND_INSN ("MXA", "", 1, FpuMeta21,
   1793 		0xf5000000, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
   1794     FCOND_INSN ("MXAS", "", 1, FpuMeta21,
   1795 		0xf5000100, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
   1796     FCOND_INSN ("MXA1", "", 1, FpuMeta21,
   1797 		0xf5000001, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
   1798     FCOND_INSN ("MXAS1", "", 1, FpuMeta21,
   1799 		0xf5000101, 0xff84211f, INSN_FPU, ENC_FEARITH, 0),
   1800 
   1801     { "MUZ", FpuMeta21,
   1802       0xf6000010, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
   1803     { "MUZS", FpuMeta21,
   1804       0xf6000110, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
   1805     { "MUZ1", FpuMeta21,
   1806       0xf6000011, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
   1807     { "MUZS1", FpuMeta21,
   1808       0xf6000111, 0xff84211d, INSN_FPU, ENC_FEARITH, 0 },
   1809 
   1810     { "RCP", FpuMeta21,
   1811       0xf7000000, 0xff84391f, INSN_FPU, ENC_FREC, 0 },
   1812     { "RSQ", FpuMeta21,
   1813       0xf7000100, 0xff84391f, INSN_FPU, ENC_FREC, 0 },
   1814 
   1815     /* FP SIMD arithmetic instructions */
   1816     { "ADDRE", FpuMeta21,
   1817       0xf4000000, 0xff8c637f, INSN_FPU, ENC_FSIMD, 0 },
   1818     { "MULRE", FpuMeta21,
   1819       0xf4000001, 0xff8c637f, INSN_FPU, ENC_FSIMD, 0 },
   1820     { "SUBRE", FpuMeta21,
   1821       0xf4000100, 0xff8c637f, INSN_FPU, ENC_FSIMD, 0 },
   1822 
   1823     /* FP memory instructions */
   1824     { "MGETD", FpuMeta21,
   1825       0xce000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
   1826     { "MGET", FpuMeta21,
   1827       0xce000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
   1828     { "MGETL", FpuMeta21,
   1829       0xcf000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
   1830 
   1831     { "MSETD", FpuMeta21,
   1832       0xbe000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
   1833     { "MSET", FpuMeta21,
   1834       0xbe000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
   1835     { "MSETL", FpuMeta21,
   1836       0xbf000000, 0xff00001f, INSN_FPU, ENC_MGET_MSET, 0 },
   1837 
   1838     /* FP accumulator memory instructions */
   1839     { "GETL", FpuMeta21,
   1840       0xcf000004, 0xffe03f9f, INSN_FPU, ENC_FGET_SET_ACF, 0 },
   1841     { "SETL", FpuMeta21,
   1842       0xbf000004, 0xffe03f9f, INSN_FPU, ENC_FGET_SET_ACF, 0 },
   1843 
   1844     /* DSP FPU data movement */
   1845     { "MOV", DspMeta21|FpuMeta21,
   1846       0x08000146, 0xfe0001ee, INSN_DSP_FPU, ENC_DALU,
   1847       DSP_ARGS_2|DSP_ARGS_DSP_SRC1 },
   1848     { "MOV", DspMeta21|FpuMeta21,
   1849       0x080001c6, 0xfe0001ee, INSN_DSP_FPU, ENC_DALU,
   1850       DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
   1851 
   1852     /* Unit-to-unit MOV */
   1853     COND_INSN ("MOV", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1854 	       0xa3000000, 0xff00021f, INSN_GP, ENC_MOV_U2U, 0),
   1855     COND_INSN ("TTMOV", "", 1, CoreMeta12|CoreMeta21,
   1856 	       0xa3000201, 0xff00021f, INSN_GP, ENC_MOV_U2U, 0),
   1857     COND_INSN ("SWAP", "", 1, CoreMeta11|CoreMeta12|CoreMeta21,
   1858 	       0xa3000200, 0xff00021f, INSN_GP, ENC_SWAP, 0),
   1859 
   1860     /* DSP memory instructions */
   1861     { "GETD", DspMeta21,
   1862       0x94000100, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 },
   1863     { "SETD", DspMeta21,
   1864       0x94000000, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 },
   1865     { "GETL", DspMeta21,
   1866       0x94000104, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 },
   1867     { "SETL", DspMeta21,
   1868       0x94000004, 0xff0001fc, INSN_DSP, ENC_DGET_SET, 0 },
   1869 
   1870     /* DSP read pipeline prime/drain */
   1871     { "MMOVD", DspMeta21,
   1872       0xca000001, 0xff00001f, INSN_DSP, ENC_MMOV, 0 },
   1873     { "MMOVL", DspMeta21,
   1874       0xcb000001, 0xff00001f, INSN_DSP, ENC_MMOV, 0 },
   1875     { "MMOVD", DspMeta21,
   1876       0xcc000001, 0xff07c067, INSN_DSP, ENC_MMOV, 0 },
   1877     { "MMOVL", DspMeta21,
   1878       0xcd000001, 0xff07c067, INSN_DSP, ENC_MMOV, 0 },
   1879 
   1880     /* DSP Template instantiation */
   1881     TEMPLATE_INSN (DspMeta21, 0x90000000, 0xff00000f, INSN_DSP),
   1882     TEMPLATE_INSN (DspMeta21, 0x93000000, 0xff0001ff, INSN_DSP),
   1883     TEMPLATE_INSN (DspMeta21, 0x95000000, 0xff00000f, INSN_DSP),
   1884 
   1885     { "AND", DspMeta21,
   1886       0x22000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
   1887     { "ANDS", DspMeta21,
   1888       0x28000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
   1889     { "ANDS", DspMeta21,
   1890       0x2a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
   1891     { "MAX", DspMeta21,
   1892       0x70000124, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
   1893     { "MIN", DspMeta21,
   1894       0x70000120, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
   1895     { "NMIN", DspMeta21,
   1896       0x7000012c, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
   1897     { "OR", DspMeta21,
   1898       0x30000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
   1899     { "OR", DspMeta21,
   1900       0x32000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
   1901     { "ORS", DspMeta21,
   1902       0x38000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
   1903     { "ORS", DspMeta21,
   1904       0x3a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
   1905     { "XOR", DspMeta21,
   1906       0x40000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
   1907     { "XOR", DspMeta21,
   1908       0x42000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
   1909     { "XORS", DspMeta21,
   1910       0x48000100, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1 },
   1911     { "XORS", DspMeta21,
   1912       0x4a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
   1913     { "ADDB8", DspMeta21,
   1914       0x20000108, 0xfe00010c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
   1915     { "ADDT8", DspMeta21,
   1916       0x2000010c, 0xfe00010c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
   1917     { "ADDSB8", DspMeta21,
   1918       0x28000108, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
   1919     { "ADDST8", DspMeta21,
   1920       0x2800010c, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
   1921     { "MULB8", DspMeta21,
   1922       0x40000108, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
   1923     { "MULT8", DspMeta21,
   1924       0x4000010c, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
   1925     { "MULSB8", DspMeta21,
   1926       0x48000108, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
   1927     { "MULST8", DspMeta21,
   1928       0x4800010c, 0xfe00012c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
   1929     { "SUBB8", DspMeta21,
   1930       0x30000108, 0xfe00010c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
   1931     { "SUBT8", DspMeta21,
   1932       0x3000010c, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
   1933     { "SUBSB8", DspMeta21,
   1934       0x38000108, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
   1935     { "SUBST8", DspMeta21,
   1936       0x3800010c, 0xfe00014c, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_SPLIT8 },
   1937     { "MUL", DspMeta21,
   1938       0x60000100, 0xfe000100, INSN_DSP, ENC_DALU,
   1939       DSP_ARGS_1|DSP_ARGS_DACC },
   1940     { "MUL", DspMeta21,
   1941       0x62000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_1|DSP_ARGS_IMM },
   1942     { "ABS", DspMeta21,
   1943       0x70000128, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
   1944     { "FFB", DspMeta21,
   1945       0x70000104, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
   1946     { "NORM", DspMeta21,
   1947       0x70000108, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
   1948     { "CMP", DspMeta21,
   1949       0x70000000, 0xfe0000ec, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM },
   1950     { "CMP", DspMeta21,
   1951       0x72000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM },
   1952     { "TST", DspMeta21,
   1953       0x78000100, 0xfe0001ec, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM },
   1954     { "TST", DspMeta21,
   1955       0x7a000003, 0xfe000003, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_IMM },
   1956     { "MOV", DspMeta21,
   1957       0x00000104, 0xfe078146, INSN_DSP, ENC_DALU,
   1958       DSP_ARGS_2|DSP_ARGS_DSP_SRC1|DSP_ARGS_DSP_SRC2|DSP_ARGS_IMM },
   1959     { "MOVS", DspMeta21,
   1960       0x08000104, 0xfe000146, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
   1961     { "MOV", DspMeta21,
   1962       0x91000000, 0xff000000, INSN_DSP, ENC_DALU,
   1963       DSP_ARGS_2|DSP_ARGS_DSP_SRC1|DSP_ARGS_IMM },
   1964     { "MOV", DspMeta21,
   1965       0x92000000, 0xff000000, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
   1966     { "NEG", DspMeta21,
   1967       0x10000104, 0xfe000146, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
   1968     { "NEGS", DspMeta21,
   1969       0x18000104, 0xfe000146, INSN_DSP, ENC_DALU, DSP_ARGS_2|DSP_ARGS_DSP_SRC2 },
   1970     { "XSDB", DspMeta21,
   1971       0xaa000100, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
   1972     { "XSD", DspMeta21,
   1973       0xaa000100, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
   1974     { "XSDW", DspMeta21,
   1975       0xaa000102, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
   1976     { "XSDSB", DspMeta21,
   1977       0xaa000108, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
   1978     { "XSDS", DspMeta21,
   1979       0xaa000108, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
   1980     { "XSDSW", DspMeta21,
   1981       0xaa00010a, 0xff0001ee, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
   1982     { "LSL", DspMeta21,
   1983       0x50000100, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
   1984     { "LSR", DspMeta21,
   1985       0x50000140, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
   1986     { "ASL", DspMeta21,
   1987       0x50000180, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
   1988     { "ASR", DspMeta21,
   1989       0x500001c0, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
   1990     { "LSL", DspMeta21,
   1991       0x54000120, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM },
   1992     { "LSR", DspMeta21,
   1993       0x54000160, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM },
   1994     { "ASL", DspMeta21,
   1995       0x540001a0, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM },
   1996     { "ASR", DspMeta21,
   1997       0x540001e0, 0xfc0001e0, INSN_DSP, ENC_DALU, DSP_ARGS_IMM },
   1998     COND_INSN ("LSL", "", 1, DspMeta21,
   1999 	       0x54000100, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
   2000     COND_INSN ("LSR", "", 1, DspMeta21,
   2001 	       0x54000140, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
   2002     COND_INSN ("ASL", "", 1, DspMeta21,
   2003 	       0x54000180, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
   2004     COND_INSN ("ASR", "", 1, DspMeta21,
   2005 	       0x540001c0, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
   2006     { "LSLS", DspMeta21,
   2007       0x58000100, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
   2008     { "LSRS", DspMeta21,
   2009       0x58000140, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
   2010     { "ASLS", DspMeta21,
   2011       0x58000180, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
   2012     { "ASRS", DspMeta21,
   2013       0x580001c0, 0xfc0001c0, INSN_DSP, ENC_DALU, 0 },
   2014     COND_INSN ("LSLS", "", 1, DspMeta21,
   2015 	       0x5c000100, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
   2016     COND_INSN ("LSRS", "", 1, DspMeta21,
   2017 	       0x5c000140, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
   2018     COND_INSN ("ASLS", "", 1, DspMeta21,
   2019 	       0x5c000180, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
   2020     COND_INSN ("ASRS", "", 1, DspMeta21,
   2021 	       0x5c0001c0, 0xfc0001fe, INSN_DSP, ENC_DALU, 0),
   2022     { "LSLS", DspMeta21,
   2023       0x5c000120, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 },
   2024     { "LSRS", DspMeta21,
   2025       0x5c000160, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 },
   2026     { "ASLS", DspMeta21,
   2027       0x5c0001a0, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 },
   2028     { "ASRS", DspMeta21,
   2029       0x5c0001e0, 0xfc0001e0, INSN_DSP, ENC_DALU, 0 },
   2030     { "RTDW", DspMeta21,
   2031       0xaa000106, 0xff00010e, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
   2032     { "RTDSW", DspMeta21,
   2033       0xaa00010e, 0xff00010e, INSN_DSP, ENC_DALU, DSP_ARGS_2 },
   2034   };
   2035 
   2036 #define UNIT_MASK                  0xf
   2037 #define SHORT_UNIT_MASK            0x3
   2038 #define EXT_BASE_REG_MASK          0x1
   2039 #define REG_MASK                  0x1f
   2040 #define CC_MASK                    0xf
   2041 #define RMASK_MASK                0x7f
   2042 #define GET_SET_IMM_MASK          0x3f
   2043 #define GET_SET_IMM_BITS             6
   2044 #define GET_SET_EXT_IMM_MASK     0xfff
   2045 #define GET_SET_EXT_IMM_BITS        12
   2046 #define DGET_SET_IMM_MASK          0x3
   2047 #define DGET_SET_IMM_BITS            2
   2048 #define MGET_MSET_MAX_REGS           8
   2049 #define MMOV_MAX_REGS                8
   2050 #define IMM16_MASK              0xffff
   2051 #define IMM16_BITS                  16
   2052 #define IMM19_MASK             0x7ffff
   2053 #define IMM19_BITS                  19
   2054 #define IMM8_MASK                 0xff
   2055 #define IMM8_BITS                    8
   2056 #define IMM24_MASK            0xffffff
   2057 #define IMM24_BITS                  24
   2058 #define IMM5_MASK                 0x1f
   2059 #define IMM5_BITS                    5
   2060 #define IMM6_MASK                 0x3f
   2061 #define IMM6_BITS                    6
   2062 #define IMM15_MASK              0x7fff
   2063 #define IMM15_BITS                  15
   2064 #define IMM4_MASK                 0x1f
   2065 #define IMM4_BITS                    4
   2066 #define CALLR_REG_MASK             0x7
   2067 #define CPC_REG_MASK               0xf
   2068 #define O2R_REG_MASK               0x7
   2069 #define ACF_PART_MASK              0x3
   2070 #define DSP_REG_MASK               0xf
   2071 #define DSP_PART_MASK             0x17
   2072 #define TEMPLATE_NUM_REGS            4
   2073 #define TEMPLATE_REGS_MASK         0xf
   2074 
   2075 #define IS_TEMPLATE_DEF(insn) (insn->dsp_daoppame_flags & DSP_DAOPPAME_TEMP)
   2076 
   2077 unsigned int metag_get_set_size_bytes (unsigned int opcode);
   2078 unsigned int metag_get_set_ext_size_bytes (unsigned int opcode);
   2079 unsigned int metag_cond_set_size_bytes (unsigned int opcode);
   2080