| /external/llvm/lib/Target/X86/ |
| X86MachineFunctionInfo.cpp | 20 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
22 unsigned SlotSize = RegInfo->getSlotSize();
24 RegInfo->X86RegisterInfo::getCalleeSavedRegs(MF);
|
| X86CallFrameOptimization.cpp | 100 const X86RegisterInfo &RegInfo,
222 const X86RegisterInfo &RegInfo =
224 SlotSize = RegInfo.getSlotSize();
261 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) {
303 if (!RegInfo.isPhysicalRegister(Reg))
305 if (RegInfo.regsOverlap(Reg, RegInfo.getStackRegister()))
309 if (RegInfo.regsOverlap(Reg, U))
323 const X86RegisterInfo &RegInfo =
349 unsigned StackPtr = RegInfo.getStackRegister()
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.h | 27 const NVPTXRegisterInfo RegInfo;
32 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
|
| NVPTXPrologEpilogPass.cpp | 112 const TargetRegisterInfo *RegInfo = Fn.getSubtarget().getRegisterInfo();
212 (RegInfo->needsStackRealignment(Fn) && MFI->getObjectIndexEnd() != 0))
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinFrameLowering.cpp | 47 const BlackfinRegisterInfo *RegInfo =
63 RegInfo->adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, -FrameSize);
85 RegInfo->loadConstant(MBB, MBBI, dl, BF::P1, -FrameSize);
95 const BlackfinRegisterInfo *RegInfo =
108 RegInfo->adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, FrameSize);
120 const BlackfinRegisterInfo *RegInfo =
124 if (RegInfo->requiresRegisterScavenging(MF)) {
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 52 const Thumb1RegisterInfo *RegInfo =
61 unsigned FramePtr = RegInfo->getFrameRegister(MF);
62 unsigned BasePtr = RegInfo->getBaseRegister();
74 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -VARegSaveSize,
79 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
147 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
160 if (RegInfo->needsStackRealignment(MF))
167 if (RegInfo->hasBasePointer(MF))
210 const Thumb1RegisterInfo *RegInfo =
217 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs()
[all...] |
| ARMFrameLowering.cpp | 34 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
43 RegInfo->needsStackRealignment(MF) ||
126 const ARMBaseRegisterInfo *RegInfo =
137 unsigned FramePtr = RegInfo->getFrameRegister(MF);
262 if (RegInfo->needsStackRealignment(MF)) {
296 if (RegInfo->hasBasePointer(MF)) {
299 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
304 RegInfo->getBaseRegister())
324 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
333 unsigned FramePtr = RegInfo->getFrameRegister(MF)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 138 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
144 RegInfo->needsStackRealignment(MF);
254 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
255 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MF);
276 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
279 if (!RegInfo->needsStackRealignment(*MF))
291 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
304 if (RegInfo->needsStackRealignment(MF))
413 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
499 const bool NeedsRealignment = RegInfo->needsStackRealignment(MF)
[all...] |
| AArch64CleanupLocalDynamicTLSPass.cpp | 119 MachineRegisterInfo &RegInfo = MF->getRegInfo();
120 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass);
|
| /external/llvm/lib/Target/Mips/ |
| MipsSERegisterInfo.cpp | 113 const MipsRegisterInfo *RegInfo =
140 else if (RegInfo->needsStackRealignment(MF)) {
181 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
182 unsigned Reg = RegInfo.createVirtualRegister(PtrRC);
|
| MipsSEFrameLowering.cpp | 75 const MipsRegisterInfo &RegInfo;
83 RegInfo(*Subtarget.getRegisterInfo()) {}
154 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
158 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
169 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
175 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
187 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
191 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
192 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
196 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0)
[all...] |
| Mips16ISelDAGToDAG.cpp | 73 MachineRegisterInfo &RegInfo = MF.getRegInfo();
79 V0 = RegInfo.createVirtualRegister(RC);
80 V1 = RegInfo.createVirtualRegister(RC);
81 V2 = RegInfo.createVirtualRegister(RC);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 93 const SparcRegisterInfo &RegInfo =
99 bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF);
158 unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true);
171 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true);
172 unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true);
234 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
238 RegInfo->needsStackRealignment(MF) ||
248 const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
266 } else if (RegInfo->needsStackRealignment(MF)) {
280 FrameReg = RegInfo->getFrameRegister(MF)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| MachineFunction.cpp | 59 RegInfo = new (Allocator) MachineRegisterInfo(*TM.getRegisterInfo());
61 RegInfo = 0;
81 if (RegInfo) {
82 RegInfo->~MachineRegisterInfo();
83 Allocator.Deallocate(RegInfo);
303 if (RegInfo && !RegInfo->livein_empty()) {
306 I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) {
315 if (RegInfo && !RegInfo->liveout_empty())
[all...] |
| MachineInstr.cpp | 52 void MachineOperand::AddRegOperandToRegInfo(MachineRegisterInfo *RegInfo) {
55 // If the reginfo pointer is null, just explicitly null out or next/prev
57 if (RegInfo == 0) {
64 MachineOperand **Head = &RegInfo->getRegUseDefListHead(getReg());
600 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo) {
603 Operands[i].AddRegOperandToRegInfo(&RegInfo);
615 MachineRegisterInfo *RegInfo = getRegInfo();
618 // be removed and re-added to RegInfo. It is storing pointers to operands.
619 bool Reallocate = RegInfo &&
626 // Remove all the implicit operands from RegInfo if they need to be shifted
[all...] |
| PrologEpilogInserter.cpp | 150 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
197 RegInfo->eliminateCallFramePseudoInstr(Fn, *I->getParent(), I);
205 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
210 const unsigned *CSRegs = RegInfo->getCalleeSavedRegs(&Fn);
231 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
253 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
256 if (RegInfo->hasReservedSpillSlot(Fn, Reg, FrameIdx)) {
565 const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
566 if (RS && TFI.hasFP(Fn) && RegInfo->useFPForScavengingIndex(Fn) &&
567 !RegInfo->needsStackRealignment(Fn))
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 56 const ThumbRegisterInfo *RegInfo =
75 emitSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount);
78 emitSPUpdate(MBB, I, TII, dl, *RegInfo, Amount);
92 const ThumbRegisterInfo *RegInfo =
107 unsigned FramePtr = RegInfo->getFrameRegister(MF);
108 unsigned BasePtr = RegInfo->getBaseRegister();
121 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
133 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
266 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
288 if (RegInfo->needsStackRealignment(MF)
[all...] |
| ARMFrameLowering.cpp | 59 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
69 RegInfo->needsStackRealignment(MF) ||
297 const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo();
311 unsigned FramePtr = RegInfo->getFrameRegister(MF);
646 if (!AFI->getNumAlignedDPRCS2Regs() && RegInfo->needsStackRealignment(MF)) {
676 if (RegInfo->hasBasePointer(MF)) {
679 TII.get(ARM::MOVr), RegInfo->getBaseRegister())
684 RegInfo->getBaseRegister())
699 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
708 unsigned FramePtr = RegInfo->getFrameRegister(MF)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZLDCleanup.cpp | 135 MachineRegisterInfo &RegInfo = MF->getRegInfo();
136 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&SystemZ::GR64BitRegClass);
|
| /external/llvm/lib/CodeGen/ |
| DetectDeadLanes.cpp | 107 const VRegInfo &RegInfo) const;
303 VRegInfo &RegInfo = VRegInfos[DefRegIdx];
304 LaneBitmask PrevDefinedLanes = RegInfo.DefinedLanes;
309 RegInfo.DefinedLanes = PrevDefinedLanes | DefinedLanes;
462 const VRegInfo &RegInfo) const {
465 return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask) == 0;
548 const VRegInfo &RegInfo = VRegInfos[RegIdx];
549 if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes == 0) {
555 if (isUndefRegAtInput(MO, RegInfo)) {
[all...] |
| MIRPrinter.cpp | 81 void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
204 const MachineRegisterInfo &RegInfo,
206 MF.IsSSA = RegInfo.isSSA();
207 MF.TracksRegLiveness = RegInfo.tracksLiveness();
208 MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
211 for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
215 if (RegInfo.getRegClassOrNull(Reg))
217 StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
218 else if (RegInfo.getRegBankOrNull(Reg))
219 VReg.Class = StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower()
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| MachineInstr.h | 441 const TargetRegisterInfo &RegInfo);
448 const TargetRegisterInfo *RegInfo,
455 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
461 const TargetRegisterInfo *RegInfo = 0);
574 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
|
| /external/llvm/lib/CodeGen/MIRParser/ |
| MIRParser.cpp | 357 MachineRegisterInfo &RegInfo = MF.getRegInfo();
358 assert(RegInfo.isSSA());
360 RegInfo.leaveSSA();
361 assert(RegInfo.tracksLiveness());
363 RegInfo.invalidateLiveness();
364 RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness);
373 Reg = RegInfo.createGenericVirtualRegister(/*Size*/ 1);
378 Reg = RegInfo.createVirtualRegister(RC);
386 Reg = RegInfo.createGenericVirtualRegister(/*Size*/ 1);
387 RegInfo.setRegBank(Reg, *RegBank)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| AlphaInstrInfo.cpp | 347 MachineRegisterInfo &RegInfo = MF->getRegInfo();
350 GlobalBaseReg = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
353 RegInfo.addLiveIn(Alpha::R29);
372 MachineRegisterInfo &RegInfo = MF->getRegInfo();
375 GlobalRetAddr = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
378 RegInfo.addLiveIn(Alpha::R26);
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86FrameLowering.cpp | 465 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
466 unsigned FramePtr = RegInfo->getFrameRegister(MF);
467 unsigned StackPtr = RegInfo->getStackRegister();
600 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
612 unsigned SlotSize = RegInfo->getSlotSize();
613 unsigned FramePtr = RegInfo->getFrameRegister(MF);
614 unsigned StackPtr = RegInfo->getStackRegister();
639 !RegInfo->needsStackRealignment(MF) &&
686 if (RegInfo->needsStackRealignment(MF))
748 if (RegInfo->needsStackRealignment(MF))
[all...] |
