/external/vixl/examples/aarch32/ |
abs.cc | 38 __ Rsb(mi, r0, r0, 0);
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/art/compiler/utils/arm/ |
assembler_arm_vixl.cc | 65 ___ Rsb(reg, reg, 0); 70 ___ Rsb(reg, reg, 0);
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assembler_arm_vixl.h | 83 WITH_FLAGS_DONT_CARE_RD_RN_OP(Rsb);
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/external/swiftshader/third_party/subzero/src/ |
IceInstARM32.h | 414 Rsb, [all...] |
IceInstARM32.cpp | 621 Asm->rsb(getDest(), getSrc(0), getSrc(1), SetFlags, getPredicate()); [all...] |
/external/vixl/test/aarch32/ |
test-disasm-a32.cc | [all...] |
test-simulator-cond-rd-rn-operand-rm-a32.cc | 130 M(Rsb) \ [all...] |
test-simulator-cond-rd-rn-operand-rm-t32.cc | 132 M(Rsb) \ [all...] |
test-simulator-cond-rd-rn-operand-const-a32.cc | 130 M(Rsb) \ [all...] |
test-simulator-cond-rd-rn-operand-const-t32.cc | 132 M(Rsb) \ [all...] |
test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 130 M(Rsb) \ [all...] |
test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 132 M(Rsb) \ [all...] |
test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 130 M(Rsb) \ [all...] |
test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 132 M(Rsb) \ [all...] |
test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc | 120 M(Rsb) \ [all...] |
test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 130 M(Rsb) \ [all...] |
/art/compiler/optimizing/ |
code_generator_arm_vixl.cc | [all...] |
/external/vixl/src/aarch32/ |
macro-assembler-aarch32.h | [all...] |