| /external/llvm/lib/Target/Lanai/ |
| LanaiTargetTransformInfo.h | 71 case ISD::SDIV:
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 147 case ISD::SDIV:
155 if (N->getOpcode() == ISD::SDIV) {
165 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 67 if ((Opcode == Instruction::SDiv || Opcode == Instruction::UDiv ||
426 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost},
430 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost},
434 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost},
438 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost},
443 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost},
447 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost},
451 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost},
455 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost},
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 339 case ISD::SDIV:
350 if (N->getOpcode() == ISD::SDIV) {
362 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
|
| /external/llvm/lib/Target/BPF/ |
| BPFISelDAGToDAG.cpp | 133 case ISD::SDIV: {
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| ISDOpcodes.h | 189 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 98 if (ISD == ISD::SDIV &&
121 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
123 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
224 { ISD::SDIV, MVT::v32i8, 32*20 },
225 { ISD::SDIV, MVT::v16i16, 16*20 },
226 { ISD::SDIV, MVT::v8i32, 8*20 },
227 { ISD::SDIV, MVT::v4i64, 4*20 },
273 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence
275 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence
282 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/arm64/ |
| anames.go | 173 "SDIV",
|
| /prebuilts/go/linux-x86/src/cmd/internal/obj/arm64/ |
| anames.go | 173 "SDIV",
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-3957855/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 200 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-3960126/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 200 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-3977809/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 200 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 200 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| /prebuilts/clang/host/linux-x86/clang-3957855/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 200 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| /prebuilts/clang/host/linux-x86/clang-3960126/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 200 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| /prebuilts/clang/host/linux-x86/clang-3977809/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 200 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 200 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
142 case ISD::SDIV:
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 99 setOperationAction(ISD::SDIV , MVT::i64, Custom);
691 case ISD::SDIV:
695 return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.getNode(), DAG, NULL)
702 case ISD::SDIV: opstr = "__divq"; break;
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 79 setOperationAction(ISD::SDIV, MVT::i16, Expand);
80 setOperationAction(ISD::SDIV, MVT::i32, Expand);
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 98 setOperationAction(ISD::SDIV, MVT::i32, Expand);
100 setOperationAction(ISD::SDIV, MVT::i64, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 182 setOperationAction(ISD::SDIV, MVT::i8, Expand);
188 setOperationAction(ISD::SDIV, MVT::i16, Expand);
194 setOperationAction(ISD::SDIV, MVT::i32, Expand);
200 setOperationAction(ISD::SDIV, MVT::i64, Expand);
206 setOperationAction(ISD::SDIV, MVT::i128, Expand);
422 setOperationAction(ISD::SDIV, VT, Expand);
[all...] |
| /external/pcre/dist2/src/sljit/ |
| sljitNativeARM_64.c | 109 #define SDIV 0x9ac00c00
[all...] |
