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      1 /*
      2  * Copyright (c) 2011 Intel Corporation. All Rights Reserved.
      3  * Copyright (c) Imagination Technologies Limited, UK
      4  *
      5  * Permission is hereby granted, free of charge, to any person obtaining a
      6  * copy of this software and associated documentation files (the
      7  * "Software"), to deal in the Software without restriction, including
      8  * without limitation the rights to use, copy, modify, merge, publish,
      9  * distribute, sub license, and/or sell copies of the Software, and to
     10  * permit persons to whom the Software is furnished to do so, subject to
     11  * the following conditions:
     12  *
     13  * The above copyright notice and this permission notice (including the
     14  * next paragraph) shall be included in all copies or substantial portions
     15  * of the Software.
     16  *
     17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
     18  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
     19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
     20  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
     21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
     22  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
     23  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
     24  */
     25 
     26 #ifndef _REGCONV_H_topazhp_multicore_regs_h
     27 #define _REGCONV_H_topazhp_multicore_regs_h
     28 
     29 #ifdef __cplusplus
     30 #include "img_types.h"
     31 #include "systemc_utils.h"
     32 #endif
     33 
     34 
     35 /* Register CR_MULTICORE_SRST */
     36 #define TOPAZHP_TOP_CR_MULTICORE_SRST 0x0000
     37 #define MASK_TOPAZHP_TOP_CR_IMG_TOPAZ_MTX_SOFT_RESET 0x00000001
     38 #define SHIFT_TOPAZHP_TOP_CR_IMG_TOPAZ_MTX_SOFT_RESET 0
     39 #define REGNUM_TOPAZHP_TOP_CR_IMG_TOPAZ_MTX_SOFT_RESET 0x0000
     40 #define SIGNED_TOPAZHP_TOP_CR_IMG_TOPAZ_MTX_SOFT_RESET 0
     41 
     42 #define MASK_TOPAZHP_TOP_CR_IMG_TOPAZ_IO_SOFT_RESET 0x00000002
     43 #define SHIFT_TOPAZHP_TOP_CR_IMG_TOPAZ_IO_SOFT_RESET 1
     44 #define REGNUM_TOPAZHP_TOP_CR_IMG_TOPAZ_IO_SOFT_RESET 0x0000
     45 #define SIGNED_TOPAZHP_TOP_CR_IMG_TOPAZ_IO_SOFT_RESET 0
     46 
     47 #define MASK_TOPAZHP_TOP_CR_IMG_TOPAZ_CORE_SOFT_RESET 0x00000004
     48 #define SHIFT_TOPAZHP_TOP_CR_IMG_TOPAZ_CORE_SOFT_RESET 2
     49 #define REGNUM_TOPAZHP_TOP_CR_IMG_TOPAZ_CORE_SOFT_RESET 0x0000
     50 #define SIGNED_TOPAZHP_TOP_CR_IMG_TOPAZ_CORE_SOFT_RESET 0
     51 
     52 /* Register CR_MULTICORE_INT_STAT */
     53 #define TOPAZHP_TOP_CR_MULTICORE_INT_STAT 0x0004
     54 #define MASK_TOPAZHP_TOP_CR_INT_STAT_DMAC 0x00000001
     55 #define SHIFT_TOPAZHP_TOP_CR_INT_STAT_DMAC 0
     56 #define REGNUM_TOPAZHP_TOP_CR_INT_STAT_DMAC 0x0004
     57 #define SIGNED_TOPAZHP_TOP_CR_INT_STAT_DMAC 0
     58 
     59 #define MASK_TOPAZHP_TOP_CR_INT_STAT_MTX 0x00000002
     60 #define SHIFT_TOPAZHP_TOP_CR_INT_STAT_MTX 1
     61 #define REGNUM_TOPAZHP_TOP_CR_INT_STAT_MTX 0x0004
     62 #define SIGNED_TOPAZHP_TOP_CR_INT_STAT_MTX 0
     63 
     64 #define MASK_TOPAZHP_TOP_CR_INT_STAT_MTX_HALT 0x00000004
     65 #define SHIFT_TOPAZHP_TOP_CR_INT_STAT_MTX_HALT 2
     66 #define REGNUM_TOPAZHP_TOP_CR_INT_STAT_MTX_HALT 0x0004
     67 #define SIGNED_TOPAZHP_TOP_CR_INT_STAT_MTX_HALT 0
     68 
     69 #define MASK_TOPAZHP_TOP_CR_INT_STAT_MMU_FAULT 0x00000008
     70 #define SHIFT_TOPAZHP_TOP_CR_INT_STAT_MMU_FAULT 3
     71 #define REGNUM_TOPAZHP_TOP_CR_INT_STAT_MMU_FAULT 0x0004
     72 #define SIGNED_TOPAZHP_TOP_CR_INT_STAT_MMU_FAULT 0
     73 
     74 #define MASK_TOPAZHP_TOP_CR_INT_STAT_MTX_CORES 0x0000FF00
     75 #define SHIFT_TOPAZHP_TOP_CR_INT_STAT_MTX_CORES 8
     76 #define REGNUM_TOPAZHP_TOP_CR_INT_STAT_MTX_CORES 0x0004
     77 #define SIGNED_TOPAZHP_TOP_CR_INT_STAT_MTX_CORES 0
     78 
     79 #define MASK_TOPAZHP_TOP_CR_INT_STAT_HOST_CORES 0x00FF0000
     80 #define SHIFT_TOPAZHP_TOP_CR_INT_STAT_HOST_CORES 16
     81 #define REGNUM_TOPAZHP_TOP_CR_INT_STAT_HOST_CORES 0x0004
     82 #define SIGNED_TOPAZHP_TOP_CR_INT_STAT_HOST_CORES 0
     83 
     84 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_MAS_MTX_INTS 0x40000000
     85 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_MAS_MTX_INTS 30
     86 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_MAS_MTX_INTS 0x0004
     87 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_MAS_MTX_INTS 0
     88 
     89 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_MAS_HOST_INTS 0x80000000
     90 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_MAS_HOST_INTS 31
     91 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_MAS_HOST_INTS 0x0004
     92 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_MAS_HOST_INTS 0
     93 
     94 /* Register CR_MULTICORE_MTX_INT_ENAB */
     95 #define TOPAZHP_TOP_CR_MULTICORE_MTX_INT_ENAB 0x0008
     96 #define MASK_TOPAZHP_TOP_CR_MTX_INTEN_DMAC 0x00000001
     97 #define SHIFT_TOPAZHP_TOP_CR_MTX_INTEN_DMAC 0
     98 #define REGNUM_TOPAZHP_TOP_CR_MTX_INTEN_DMAC 0x0008
     99 #define SIGNED_TOPAZHP_TOP_CR_MTX_INTEN_DMAC 0
    100 
    101 #define MASK_TOPAZHP_TOP_CR_MTX_INTEN_MTX 0x00000002
    102 #define SHIFT_TOPAZHP_TOP_CR_MTX_INTEN_MTX 1
    103 #define REGNUM_TOPAZHP_TOP_CR_MTX_INTEN_MTX 0x0008
    104 #define SIGNED_TOPAZHP_TOP_CR_MTX_INTEN_MTX 0
    105 
    106 #define MASK_TOPAZHP_TOP_CR_MTX_INTEN_MTX_HALT 0x00000004
    107 #define SHIFT_TOPAZHP_TOP_CR_MTX_INTEN_MTX_HALT 2
    108 #define REGNUM_TOPAZHP_TOP_CR_MTX_INTEN_MTX_HALT 0x0008
    109 #define SIGNED_TOPAZHP_TOP_CR_MTX_INTEN_MTX_HALT 0
    110 
    111 #define MASK_TOPAZHP_TOP_CR_MTX_INTEN_MMU_FAULT 0x00000008
    112 #define SHIFT_TOPAZHP_TOP_CR_MTX_INTEN_MMU_FAULT 3
    113 #define REGNUM_TOPAZHP_TOP_CR_MTX_INTEN_MMU_FAULT 0x0008
    114 #define SIGNED_TOPAZHP_TOP_CR_MTX_INTEN_MMU_FAULT 0
    115 
    116 #define MASK_TOPAZHP_TOP_CR_MTX_INTEN_MTX_CORES 0x0000FF00
    117 #define SHIFT_TOPAZHP_TOP_CR_MTX_INTEN_MTX_CORES 8
    118 #define REGNUM_TOPAZHP_TOP_CR_MTX_INTEN_MTX_CORES 0x0008
    119 #define SIGNED_TOPAZHP_TOP_CR_MTX_INTEN_MTX_CORES 0
    120 
    121 #define MASK_TOPAZHP_TOP_CR_MTX_INTEN_HOST_CORES 0x00FF0000
    122 #define SHIFT_TOPAZHP_TOP_CR_MTX_INTEN_HOST_CORES 16
    123 #define REGNUM_TOPAZHP_TOP_CR_MTX_INTEN_HOST_CORES 0x0008
    124 #define SIGNED_TOPAZHP_TOP_CR_MTX_INTEN_HOST_CORES 0
    125 
    126 #define MASK_TOPAZHP_TOP_CR_MTX_TOPAZHP_MAS_INTEN 0x40000000
    127 #define SHIFT_TOPAZHP_TOP_CR_MTX_TOPAZHP_MAS_INTEN 30
    128 #define REGNUM_TOPAZHP_TOP_CR_MTX_TOPAZHP_MAS_INTEN 0x0008
    129 #define SIGNED_TOPAZHP_TOP_CR_MTX_TOPAZHP_MAS_INTEN 0
    130 
    131 /* Register CR_MULTICORE_HOST_INT_ENAB */
    132 #define TOPAZHP_TOP_CR_MULTICORE_HOST_INT_ENAB 0x000C
    133 #define MASK_TOPAZHP_TOP_CR_HOST_INTEN_DMAC 0x00000001
    134 #define SHIFT_TOPAZHP_TOP_CR_HOST_INTEN_DMAC 0
    135 #define REGNUM_TOPAZHP_TOP_CR_HOST_INTEN_DMAC 0x000C
    136 #define SIGNED_TOPAZHP_TOP_CR_HOST_INTEN_DMAC 0
    137 
    138 #define MASK_TOPAZHP_TOP_CR_HOST_INTEN_MTX 0x00000002
    139 #define SHIFT_TOPAZHP_TOP_CR_HOST_INTEN_MTX 1
    140 #define REGNUM_TOPAZHP_TOP_CR_HOST_INTEN_MTX 0x000C
    141 #define SIGNED_TOPAZHP_TOP_CR_HOST_INTEN_MTX 0
    142 
    143 #define MASK_TOPAZHP_TOP_CR_HOST_INTEN_MTX_HALT 0x00000004
    144 #define SHIFT_TOPAZHP_TOP_CR_HOST_INTEN_MTX_HALT 2
    145 #define REGNUM_TOPAZHP_TOP_CR_HOST_INTEN_MTX_HALT 0x000C
    146 #define SIGNED_TOPAZHP_TOP_CR_HOST_INTEN_MTX_HALT 0
    147 
    148 #define MASK_TOPAZHP_TOP_CR_HOST_INTEN_MMU_FAULT 0x00000008
    149 #define SHIFT_TOPAZHP_TOP_CR_HOST_INTEN_MMU_FAULT 3
    150 #define REGNUM_TOPAZHP_TOP_CR_HOST_INTEN_MMU_FAULT 0x000C
    151 #define SIGNED_TOPAZHP_TOP_CR_HOST_INTEN_MMU_FAULT 0
    152 
    153 #define MASK_TOPAZHP_TOP_CR_HOST_INTEN_MTX_CORES 0x0000FF00
    154 #define SHIFT_TOPAZHP_TOP_CR_HOST_INTEN_MTX_CORES 8
    155 #define REGNUM_TOPAZHP_TOP_CR_HOST_INTEN_MTX_CORES 0x000C
    156 #define SIGNED_TOPAZHP_TOP_CR_HOST_INTEN_MTX_CORES 0
    157 
    158 #define MASK_TOPAZHP_TOP_CR_HOST_INTEN_HOST_CORES 0x00FF0000
    159 #define SHIFT_TOPAZHP_TOP_CR_HOST_INTEN_HOST_CORES 16
    160 #define REGNUM_TOPAZHP_TOP_CR_HOST_INTEN_HOST_CORES 0x000C
    161 #define SIGNED_TOPAZHP_TOP_CR_HOST_INTEN_HOST_CORES 0
    162 
    163 #define MASK_TOPAZHP_TOP_CR_HOST_TOPAZHP_MAS_INTEN 0x80000000
    164 #define SHIFT_TOPAZHP_TOP_CR_HOST_TOPAZHP_MAS_INTEN 31
    165 #define REGNUM_TOPAZHP_TOP_CR_HOST_TOPAZHP_MAS_INTEN 0x000C
    166 #define SIGNED_TOPAZHP_TOP_CR_HOST_TOPAZHP_MAS_INTEN 0
    167 
    168 /* Register CR_MULTICORE_INT_CLEAR */
    169 #define TOPAZHP_TOP_CR_MULTICORE_INT_CLEAR 0x0010
    170 #define MASK_TOPAZHP_TOP_CR_INTCLR_DMAC 0x00000001
    171 #define SHIFT_TOPAZHP_TOP_CR_INTCLR_DMAC 0
    172 #define REGNUM_TOPAZHP_TOP_CR_INTCLR_DMAC 0x0010
    173 #define SIGNED_TOPAZHP_TOP_CR_INTCLR_DMAC 0
    174 
    175 #define MASK_TOPAZHP_TOP_CR_INTCLR_MTX 0x00000002
    176 #define SHIFT_TOPAZHP_TOP_CR_INTCLR_MTX 1
    177 #define REGNUM_TOPAZHP_TOP_CR_INTCLR_MTX 0x0010
    178 #define SIGNED_TOPAZHP_TOP_CR_INTCLR_MTX 0
    179 
    180 #define MASK_TOPAZHP_TOP_CR_INTCLR_MTX_HALT 0x00000004
    181 #define SHIFT_TOPAZHP_TOP_CR_INTCLR_MTX_HALT 2
    182 #define REGNUM_TOPAZHP_TOP_CR_INTCLR_MTX_HALT 0x0010
    183 #define SIGNED_TOPAZHP_TOP_CR_INTCLR_MTX_HALT 0
    184 
    185 #define MASK_TOPAZHP_TOP_CR_INTCLR_MMU_FAULT 0x00000008
    186 #define SHIFT_TOPAZHP_TOP_CR_INTCLR_MMU_FAULT 3
    187 #define REGNUM_TOPAZHP_TOP_CR_INTCLR_MMU_FAULT 0x0010
    188 #define SIGNED_TOPAZHP_TOP_CR_INTCLR_MMU_FAULT 0
    189 
    190 /* Register CR_MULTICORE_MAN_CLK_GATE */
    191 #define TOPAZHP_TOP_CR_MULTICORE_MAN_CLK_GATE 0x0014
    192 #define MASK_TOPAZHP_TOP_CR_TOPAZ_MTX_MAN_CLK_GATE 0x00000002
    193 #define SHIFT_TOPAZHP_TOP_CR_TOPAZ_MTX_MAN_CLK_GATE 1
    194 #define REGNUM_TOPAZHP_TOP_CR_TOPAZ_MTX_MAN_CLK_GATE 0x0014
    195 #define SIGNED_TOPAZHP_TOP_CR_TOPAZ_MTX_MAN_CLK_GATE 0
    196 
    197 /* Register CR_TOPAZ_MTX_C_RATIO */
    198 #define TOPAZHP_TOP_CR_TOPAZ_MTX_C_RATIO 0x0018
    199 #define MASK_TOPAZHP_TOP_CR_MTX_C_RATIO 0x00000003
    200 #define SHIFT_TOPAZHP_TOP_CR_MTX_C_RATIO 0
    201 #define REGNUM_TOPAZHP_TOP_CR_MTX_C_RATIO 0x0018
    202 #define SIGNED_TOPAZHP_TOP_CR_MTX_C_RATIO 0
    203 
    204 /* Register CR_MMU_STATUS */
    205 #define TOPAZHP_TOP_CR_MMU_STATUS   0x001C
    206 #define MASK_TOPAZHP_TOP_CR_MMU_PF_N_RW 0x00000001
    207 #define SHIFT_TOPAZHP_TOP_CR_MMU_PF_N_RW 0
    208 #define REGNUM_TOPAZHP_TOP_CR_MMU_PF_N_RW 0x001C
    209 #define SIGNED_TOPAZHP_TOP_CR_MMU_PF_N_RW 0
    210 
    211 #define MASK_TOPAZHP_TOP_CR_MMU_FAULT_ADDR 0xFFFFF000
    212 #define SHIFT_TOPAZHP_TOP_CR_MMU_FAULT_ADDR 12
    213 #define REGNUM_TOPAZHP_TOP_CR_MMU_FAULT_ADDR 0x001C
    214 #define SIGNED_TOPAZHP_TOP_CR_MMU_FAULT_ADDR 0
    215 
    216 /* Register CR_MMU_MEM_REQ */
    217 #define TOPAZHP_TOP_CR_MMU_MEM_REQ  0x0020
    218 #define MASK_TOPAZHP_TOP_CR_MEM_REQ_STAT_READS 0x000000FF
    219 #define SHIFT_TOPAZHP_TOP_CR_MEM_REQ_STAT_READS 0
    220 #define REGNUM_TOPAZHP_TOP_CR_MEM_REQ_STAT_READS 0x0020
    221 #define SIGNED_TOPAZHP_TOP_CR_MEM_REQ_STAT_READS 0
    222 
    223 /* Register CR_MMU_CONTROL0 */
    224 #define TOPAZHP_TOP_CR_MMU_CONTROL0 0x0024
    225 #define MASK_TOPAZHP_TOP_CR_MMU_NOREORDER 0x00000001
    226 #define SHIFT_TOPAZHP_TOP_CR_MMU_NOREORDER 0
    227 #define REGNUM_TOPAZHP_TOP_CR_MMU_NOREORDER 0x0024
    228 #define SIGNED_TOPAZHP_TOP_CR_MMU_NOREORDER 0
    229 
    230 #define MASK_TOPAZHP_TOP_CR_MMU_PAUSE 0x00000002
    231 #define SHIFT_TOPAZHP_TOP_CR_MMU_PAUSE 1
    232 #define REGNUM_TOPAZHP_TOP_CR_MMU_PAUSE 0x0024
    233 #define SIGNED_TOPAZHP_TOP_CR_MMU_PAUSE 0
    234 
    235 #define MASK_TOPAZHP_TOP_CR_MMU_FLUSH 0x00000004
    236 #define SHIFT_TOPAZHP_TOP_CR_MMU_FLUSH 2
    237 #define REGNUM_TOPAZHP_TOP_CR_MMU_FLUSH 0x0024
    238 #define SIGNED_TOPAZHP_TOP_CR_MMU_FLUSH 0
    239 
    240 #define MASK_TOPAZHP_TOP_CR_MMU_INVALDC 0x00000008
    241 #define SHIFT_TOPAZHP_TOP_CR_MMU_INVALDC 3
    242 #define REGNUM_TOPAZHP_TOP_CR_MMU_INVALDC 0x0024
    243 #define SIGNED_TOPAZHP_TOP_CR_MMU_INVALDC 0
    244 
    245 #define MASK_TOPAZHP_TOP_CR_FLOWRATE_TOPAZ 0x00000700
    246 #define SHIFT_TOPAZHP_TOP_CR_FLOWRATE_TOPAZ 8
    247 #define REGNUM_TOPAZHP_TOP_CR_FLOWRATE_TOPAZ 0x0024
    248 #define SIGNED_TOPAZHP_TOP_CR_FLOWRATE_TOPAZ 0
    249 
    250 #define MASK_TOPAZHP_TOP_CR_MMU_BYPASS_TOPAZ 0x00010000
    251 #define SHIFT_TOPAZHP_TOP_CR_MMU_BYPASS_TOPAZ 16
    252 #define REGNUM_TOPAZHP_TOP_CR_MMU_BYPASS_TOPAZ 0x0024
    253 #define SIGNED_TOPAZHP_TOP_CR_MMU_BYPASS_TOPAZ 0
    254 
    255 /* Register CR_MMU_CONTROL1 */
    256 #define TOPAZHP_TOP_CR_MMU_CONTROL1 0x0028
    257 #define MASK_TOPAZHP_TOP_CR_MMU_TTE_THRESHOLD 0x00000FFF
    258 #define SHIFT_TOPAZHP_TOP_CR_MMU_TTE_THRESHOLD 0
    259 #define REGNUM_TOPAZHP_TOP_CR_MMU_TTE_THRESHOLD 0x0028
    260 #define SIGNED_TOPAZHP_TOP_CR_MMU_TTE_THRESHOLD 0
    261 
    262 #define MASK_TOPAZHP_TOP_CR_MMU_ADT_TTE 0x000FF000
    263 #define SHIFT_TOPAZHP_TOP_CR_MMU_ADT_TTE 12
    264 #define REGNUM_TOPAZHP_TOP_CR_MMU_ADT_TTE 0x0028
    265 #define SIGNED_TOPAZHP_TOP_CR_MMU_ADT_TTE 0
    266 
    267 #define MASK_TOPAZHP_TOP_CR_MMU_BEST_COUNT 0x0FF00000
    268 #define SHIFT_TOPAZHP_TOP_CR_MMU_BEST_COUNT 20
    269 #define REGNUM_TOPAZHP_TOP_CR_MMU_BEST_COUNT 0x0028
    270 #define SIGNED_TOPAZHP_TOP_CR_MMU_BEST_COUNT 0
    271 
    272 #define MASK_TOPAZHP_TOP_CR_MMU_PAGE_SIZE 0xF0000000
    273 #define SHIFT_TOPAZHP_TOP_CR_MMU_PAGE_SIZE 28
    274 #define REGNUM_TOPAZHP_TOP_CR_MMU_PAGE_SIZE 0x0028
    275 #define SIGNED_TOPAZHP_TOP_CR_MMU_PAGE_SIZE 0
    276 
    277 /* Register CR_MMU_CONTROL2 */
    278 #define TOPAZHP_TOP_CR_MMU_CONTROL2 0x002C
    279 #define MASK_TOPAZHP_TOP_CR_MMU_ENABLE_36BIT_ADDRESSING 0x00000001
    280 #define SHIFT_TOPAZHP_TOP_CR_MMU_ENABLE_36BIT_ADDRESSING 0
    281 #define REGNUM_TOPAZHP_TOP_CR_MMU_ENABLE_36BIT_ADDRESSING 0x002C
    282 #define SIGNED_TOPAZHP_TOP_CR_MMU_ENABLE_36BIT_ADDRESSING 0
    283 
    284 #define MASK_TOPAZHP_TOP_CR_MMU_TILING_SCHEME 0x00000008
    285 #define SHIFT_TOPAZHP_TOP_CR_MMU_TILING_SCHEME 3
    286 #define REGNUM_TOPAZHP_TOP_CR_MMU_TILING_SCHEME 0x002C
    287 #define SIGNED_TOPAZHP_TOP_CR_MMU_TILING_SCHEME 0
    288 
    289 /* Register CR_MMU_DIR_LIST_BASE_0 */
    290 #define TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE_0 0x0030
    291 #define MASK_TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE_ADDR_00 0xFFFFFFF0
    292 #define SHIFT_TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE_ADDR_00 4
    293 #define REGNUM_TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE_ADDR_00 0x0030
    294 #define SIGNED_TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE_ADDR_00 0
    295 
    296 /* Register CR_MMU_TILE_0 */
    297 #define TOPAZHP_TOP_CR_MMU_TILE_0   0x0038
    298 #define MASK_TOPAZHP_TOP_CR_TILE_MIN_ADDR_00 0x00000FFF
    299 #define SHIFT_TOPAZHP_TOP_CR_TILE_MIN_ADDR_00 0
    300 #define REGNUM_TOPAZHP_TOP_CR_TILE_MIN_ADDR_00 0x0038
    301 #define SIGNED_TOPAZHP_TOP_CR_TILE_MIN_ADDR_00 0
    302 
    303 #define MASK_TOPAZHP_TOP_CR_TILE_MAX_ADDR_00 0x00FFF000
    304 #define SHIFT_TOPAZHP_TOP_CR_TILE_MAX_ADDR_00 12
    305 #define REGNUM_TOPAZHP_TOP_CR_TILE_MAX_ADDR_00 0x0038
    306 #define SIGNED_TOPAZHP_TOP_CR_TILE_MAX_ADDR_00 0
    307 
    308 #define MASK_TOPAZHP_TOP_CR_TILE_STRIDE_00 0x07000000
    309 #define SHIFT_TOPAZHP_TOP_CR_TILE_STRIDE_00 24
    310 #define REGNUM_TOPAZHP_TOP_CR_TILE_STRIDE_00 0x0038
    311 #define SIGNED_TOPAZHP_TOP_CR_TILE_STRIDE_00 0
    312 
    313 #define MASK_TOPAZHP_TOP_CR_TILE_ENABLE_00 0x10000000
    314 #define SHIFT_TOPAZHP_TOP_CR_TILE_ENABLE_00 28
    315 #define REGNUM_TOPAZHP_TOP_CR_TILE_ENABLE_00 0x0038
    316 #define SIGNED_TOPAZHP_TOP_CR_TILE_ENABLE_00 0
    317 
    318 /* Register CR_MMU_TILE_1 */
    319 #define TOPAZHP_TOP_CR_MMU_TILE_1   0x003C
    320 #define MASK_TOPAZHP_TOP_CR_TILE_MIN_ADDR_01 0x00000FFF
    321 #define SHIFT_TOPAZHP_TOP_CR_TILE_MIN_ADDR_01 0
    322 #define REGNUM_TOPAZHP_TOP_CR_TILE_MIN_ADDR_01 0x003C
    323 #define SIGNED_TOPAZHP_TOP_CR_TILE_MIN_ADDR_01 0
    324 
    325 #define MASK_TOPAZHP_TOP_CR_TILE_MAX_ADDR_01 0x00FFF000
    326 #define SHIFT_TOPAZHP_TOP_CR_TILE_MAX_ADDR_01 12
    327 #define REGNUM_TOPAZHP_TOP_CR_TILE_MAX_ADDR_01 0x003C
    328 #define SIGNED_TOPAZHP_TOP_CR_TILE_MAX_ADDR_01 0
    329 
    330 #define MASK_TOPAZHP_TOP_CR_TILE_STRIDE_01 0x07000000
    331 #define SHIFT_TOPAZHP_TOP_CR_TILE_STRIDE_01 24
    332 #define REGNUM_TOPAZHP_TOP_CR_TILE_STRIDE_01 0x003C
    333 #define SIGNED_TOPAZHP_TOP_CR_TILE_STRIDE_01 0
    334 
    335 #define MASK_TOPAZHP_TOP_CR_TILE_ENABLE_01 0x10000000
    336 #define SHIFT_TOPAZHP_TOP_CR_TILE_ENABLE_01 28
    337 #define REGNUM_TOPAZHP_TOP_CR_TILE_ENABLE_01 0x003C
    338 #define SIGNED_TOPAZHP_TOP_CR_TILE_ENABLE_01 0
    339 
    340 /* Register CR_MTX_DEBUG_MSTR */
    341 #define TOPAZHP_TOP_CR_MTX_DEBUG_MSTR 0x0044
    342 #define MASK_TOPAZHP_TOP_CR_MTX_MSTR_DBG_GPIO_IN 0x00000003
    343 #define SHIFT_TOPAZHP_TOP_CR_MTX_MSTR_DBG_GPIO_IN 0
    344 #define REGNUM_TOPAZHP_TOP_CR_MTX_MSTR_DBG_GPIO_IN 0x0044
    345 #define SIGNED_TOPAZHP_TOP_CR_MTX_MSTR_DBG_GPIO_IN 0
    346 
    347 #define MASK_TOPAZHP_TOP_CR_MTX_MSTR_DBG_IS_SLAVE 0x00000004
    348 #define SHIFT_TOPAZHP_TOP_CR_MTX_MSTR_DBG_IS_SLAVE 2
    349 #define REGNUM_TOPAZHP_TOP_CR_MTX_MSTR_DBG_IS_SLAVE 0x0044
    350 #define SIGNED_TOPAZHP_TOP_CR_MTX_MSTR_DBG_IS_SLAVE 0
    351 
    352 #define MASK_TOPAZHP_TOP_CR_MTX_MSTR_DBG_GPIO_OUT 0x00000018
    353 #define SHIFT_TOPAZHP_TOP_CR_MTX_MSTR_DBG_GPIO_OUT 3
    354 #define REGNUM_TOPAZHP_TOP_CR_MTX_MSTR_DBG_GPIO_OUT 0x0044
    355 #define SIGNED_TOPAZHP_TOP_CR_MTX_MSTR_DBG_GPIO_OUT 0
    356 
    357 #define MASK_TOPAZHP_TOP_CR_MTX_MSTR_RAM_BANKS 0x00000F00
    358 #define SHIFT_TOPAZHP_TOP_CR_MTX_MSTR_RAM_BANKS 8
    359 #define REGNUM_TOPAZHP_TOP_CR_MTX_MSTR_RAM_BANKS 0x0044
    360 #define SIGNED_TOPAZHP_TOP_CR_MTX_MSTR_RAM_BANKS 0
    361 
    362 #define MASK_TOPAZHP_TOP_CR_MTX_MSTR_RAM_BANK_SIZE 0x000F0000
    363 #define SHIFT_TOPAZHP_TOP_CR_MTX_MSTR_RAM_BANK_SIZE 16
    364 #define REGNUM_TOPAZHP_TOP_CR_MTX_MSTR_RAM_BANK_SIZE 0x0044
    365 #define SIGNED_TOPAZHP_TOP_CR_MTX_MSTR_RAM_BANK_SIZE 0
    366 
    367 #define MASK_TOPAZHP_TOP_CR_MTX_MSTR_LAST_RAM_BANK_SIZE 0x0F000000
    368 #define SHIFT_TOPAZHP_TOP_CR_MTX_MSTR_LAST_RAM_BANK_SIZE 24
    369 #define REGNUM_TOPAZHP_TOP_CR_MTX_MSTR_LAST_RAM_BANK_SIZE 0x0044
    370 #define SIGNED_TOPAZHP_TOP_CR_MTX_MSTR_LAST_RAM_BANK_SIZE 0
    371 
    372 /* Register CR_MTX_DEBUG_SLV */
    373 #define TOPAZHP_TOP_CR_MTX_DEBUG_SLV 0x0048
    374 #define MASK_TOPAZHP_TOP_CR_MTX_SLV_DBG_GPIO_IN 0x00000003
    375 #define SHIFT_TOPAZHP_TOP_CR_MTX_SLV_DBG_GPIO_IN 0
    376 #define REGNUM_TOPAZHP_TOP_CR_MTX_SLV_DBG_GPIO_IN 0x0048
    377 #define SIGNED_TOPAZHP_TOP_CR_MTX_SLV_DBG_GPIO_IN 0
    378 
    379 #define MASK_TOPAZHP_TOP_CR_MTX_SLV_DBG_IS_SLAVE 0x00000004
    380 #define SHIFT_TOPAZHP_TOP_CR_MTX_SLV_DBG_IS_SLAVE 2
    381 #define REGNUM_TOPAZHP_TOP_CR_MTX_SLV_DBG_IS_SLAVE 0x0048
    382 #define SIGNED_TOPAZHP_TOP_CR_MTX_SLV_DBG_IS_SLAVE 0
    383 
    384 #define MASK_TOPAZHP_TOP_CR_MTX_SLV_DBG_GPIO_OUT 0x00000018
    385 #define SHIFT_TOPAZHP_TOP_CR_MTX_SLV_DBG_GPIO_OUT 3
    386 #define REGNUM_TOPAZHP_TOP_CR_MTX_SLV_DBG_GPIO_OUT 0x0048
    387 #define SIGNED_TOPAZHP_TOP_CR_MTX_SLV_DBG_GPIO_OUT 0
    388 
    389 #define MASK_TOPAZHP_TOP_CR_MTX_SLV_RAM_BANKS 0x00000F00
    390 #define SHIFT_TOPAZHP_TOP_CR_MTX_SLV_RAM_BANKS 8
    391 #define REGNUM_TOPAZHP_TOP_CR_MTX_SLV_RAM_BANKS 0x0048
    392 #define SIGNED_TOPAZHP_TOP_CR_MTX_SLV_RAM_BANKS 0
    393 
    394 #define MASK_TOPAZHP_TOP_CR_MTX_SLV_RAM_BANK_SIZE 0x000F0000
    395 #define SHIFT_TOPAZHP_TOP_CR_MTX_SLV_RAM_BANK_SIZE 16
    396 #define REGNUM_TOPAZHP_TOP_CR_MTX_SLV_RAM_BANK_SIZE 0x0048
    397 #define SIGNED_TOPAZHP_TOP_CR_MTX_SLV_RAM_BANK_SIZE 0
    398 
    399 #define MASK_TOPAZHP_TOP_CR_MTX_SLV_LAST_RAM_BANK_SIZE 0x0F000000
    400 #define SHIFT_TOPAZHP_TOP_CR_MTX_SLV_LAST_RAM_BANK_SIZE 24
    401 #define REGNUM_TOPAZHP_TOP_CR_MTX_SLV_LAST_RAM_BANK_SIZE 0x0048
    402 #define SIGNED_TOPAZHP_TOP_CR_MTX_SLV_LAST_RAM_BANK_SIZE 0
    403 
    404 /* Register CR_MULTICORE_CORE_SEL_0 */
    405 #define TOPAZHP_TOP_CR_MULTICORE_CORE_SEL_0 0x0050
    406 #define MASK_TOPAZHP_TOP_CR_DMAC_MTX_SELECT 0x00000007
    407 #define SHIFT_TOPAZHP_TOP_CR_DMAC_MTX_SELECT 0
    408 #define REGNUM_TOPAZHP_TOP_CR_DMAC_MTX_SELECT 0x0050
    409 #define SIGNED_TOPAZHP_TOP_CR_DMAC_MTX_SELECT 0
    410 
    411 #define MASK_TOPAZHP_TOP_CR_WRITES_MTX_ALL 0x40000000
    412 #define SHIFT_TOPAZHP_TOP_CR_WRITES_MTX_ALL 30
    413 #define REGNUM_TOPAZHP_TOP_CR_WRITES_MTX_ALL 0x0050
    414 #define SIGNED_TOPAZHP_TOP_CR_WRITES_MTX_ALL 0
    415 
    416 #define MASK_TOPAZHP_TOP_CR_WRITES_CORE_ALL 0x80000000
    417 #define SHIFT_TOPAZHP_TOP_CR_WRITES_CORE_ALL 31
    418 #define REGNUM_TOPAZHP_TOP_CR_WRITES_CORE_ALL 0x0050
    419 #define SIGNED_TOPAZHP_TOP_CR_WRITES_CORE_ALL 0
    420 
    421 /* Register CR_MULTICORE_CORE_SEL_1 */
    422 #define TOPAZHP_TOP_CR_MULTICORE_CORE_SEL_1 0x0054
    423 #define MASK_TOPAZHP_TOP_CR_RTM_PORT_CORE_SELECT 0x0000001F
    424 #define SHIFT_TOPAZHP_TOP_CR_RTM_PORT_CORE_SELECT 0
    425 #define REGNUM_TOPAZHP_TOP_CR_RTM_PORT_CORE_SELECT 0x0054
    426 #define SIGNED_TOPAZHP_TOP_CR_RTM_PORT_CORE_SELECT 0
    427 
    428 /* Register CR_MULTICORE_HW_CFG */
    429 #define TOPAZHP_TOP_CR_MULTICORE_HW_CFG 0x0058
    430 #define MASK_TOPAZHP_TOP_CR_NUM_CORES_SUPPORTED 0x0000001F
    431 #define SHIFT_TOPAZHP_TOP_CR_NUM_CORES_SUPPORTED 0
    432 #define REGNUM_TOPAZHP_TOP_CR_NUM_CORES_SUPPORTED 0x0058
    433 #define SIGNED_TOPAZHP_TOP_CR_NUM_CORES_SUPPORTED 0
    434 
    435 #define MASK_TOPAZHP_TOP_CR_NUM_MTX_SUPPORTED 0x00000700
    436 #define SHIFT_TOPAZHP_TOP_CR_NUM_MTX_SUPPORTED 8
    437 #define REGNUM_TOPAZHP_TOP_CR_NUM_MTX_SUPPORTED 0x0058
    438 #define SIGNED_TOPAZHP_TOP_CR_NUM_MTX_SUPPORTED 0
    439 
    440 #define MASK_TOPAZHP_TOP_CR_NUM_CORES_PER_MTX 0x00070000
    441 #define SHIFT_TOPAZHP_TOP_CR_NUM_CORES_PER_MTX 16
    442 #define REGNUM_TOPAZHP_TOP_CR_NUM_CORES_PER_MTX 0x0058
    443 #define SIGNED_TOPAZHP_TOP_CR_NUM_CORES_PER_MTX 0
    444 
    445 #define MASK_TOPAZHP_TOP_CR_EXTENDED_ADDR_RANGE 0x0F000000
    446 #define SHIFT_TOPAZHP_TOP_CR_EXTENDED_ADDR_RANGE 24
    447 #define REGNUM_TOPAZHP_TOP_CR_EXTENDED_ADDR_RANGE 0x0058
    448 #define SIGNED_TOPAZHP_TOP_CR_EXTENDED_ADDR_RANGE 0
    449 
    450 /* Register CR_MULTICORE_CMD_FIFO_WRITE */
    451 #define TOPAZHP_TOP_CR_MULTICORE_CMD_FIFO_WRITE 0x0060
    452 #define MASK_TOPAZHP_TOP_CR_CMD_FIFO_WDATA 0xFFFFFFFF
    453 #define SHIFT_TOPAZHP_TOP_CR_CMD_FIFO_WDATA 0
    454 #define REGNUM_TOPAZHP_TOP_CR_CMD_FIFO_WDATA 0x0060
    455 #define SIGNED_TOPAZHP_TOP_CR_CMD_FIFO_WDATA 0
    456 
    457 /* Register CR_MULTICORE_CMD_FIFO_WRITE_SPACE */
    458 #define TOPAZHP_TOP_CR_MULTICORE_CMD_FIFO_WRITE_SPACE 0x0064
    459 #define MASK_TOPAZHP_TOP_CR_CMD_FIFO_SPACE 0x000000FF
    460 #define SHIFT_TOPAZHP_TOP_CR_CMD_FIFO_SPACE 0
    461 #define REGNUM_TOPAZHP_TOP_CR_CMD_FIFO_SPACE 0x0064
    462 #define SIGNED_TOPAZHP_TOP_CR_CMD_FIFO_SPACE 0
    463 
    464 #define MASK_TOPAZHP_TOP_CR_CMD_FIFO_FULL 0x00000100
    465 #define SHIFT_TOPAZHP_TOP_CR_CMD_FIFO_FULL 8
    466 #define REGNUM_TOPAZHP_TOP_CR_CMD_FIFO_FULL 0x0064
    467 #define SIGNED_TOPAZHP_TOP_CR_CMD_FIFO_FULL 0
    468 
    469 /* Register CR_TOPAZ_CMD_FIFO_READ */
    470 #define TOPAZHP_TOP_CR_TOPAZ_CMD_FIFO_READ 0x0070
    471 #define MASK_TOPAZHP_TOP_CR_CMD_FIFO_RDATA 0xFFFFFFFF
    472 #define SHIFT_TOPAZHP_TOP_CR_CMD_FIFO_RDATA 0
    473 #define REGNUM_TOPAZHP_TOP_CR_CMD_FIFO_RDATA 0x0070
    474 #define SIGNED_TOPAZHP_TOP_CR_CMD_FIFO_RDATA 0
    475 
    476 /* Register CR_TOPAZ_CMD_FIFO_READ_AVAILABLE */
    477 #define TOPAZHP_TOP_CR_TOPAZ_CMD_FIFO_READ_AVAILABLE 0x0074
    478 #define MASK_TOPAZHP_TOP_CR_CMD_FIFO_QUANTITY 0x000000FF
    479 #define SHIFT_TOPAZHP_TOP_CR_CMD_FIFO_QUANTITY 0
    480 #define REGNUM_TOPAZHP_TOP_CR_CMD_FIFO_QUANTITY 0x0074
    481 #define SIGNED_TOPAZHP_TOP_CR_CMD_FIFO_QUANTITY 0
    482 
    483 #define MASK_TOPAZHP_TOP_CR_CMD_FIFO_NOTEMPTY 0x00000100
    484 #define SHIFT_TOPAZHP_TOP_CR_CMD_FIFO_NOTEMPTY 8
    485 #define REGNUM_TOPAZHP_TOP_CR_CMD_FIFO_NOTEMPTY 0x0074
    486 #define SIGNED_TOPAZHP_TOP_CR_CMD_FIFO_NOTEMPTY 0
    487 
    488 /* Register CR_TOPAZ_CMD_FIFO_FLUSH */
    489 #define TOPAZHP_TOP_CR_TOPAZ_CMD_FIFO_FLUSH 0x0078
    490 #define MASK_TOPAZHP_TOP_CR_CMD_FIFO_FLUSH 0x00000001
    491 #define SHIFT_TOPAZHP_TOP_CR_CMD_FIFO_FLUSH 0
    492 #define REGNUM_TOPAZHP_TOP_CR_CMD_FIFO_FLUSH 0x0078
    493 #define SIGNED_TOPAZHP_TOP_CR_CMD_FIFO_FLUSH 0
    494 
    495 /* Register CR_MMU_TILE_EXT_0 */
    496 #define TOPAZHP_TOP_CR_MMU_TILE_EXT_0 0x0080
    497 #define MASK_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT_00 0x000000FF
    498 #define SHIFT_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT_00 0
    499 #define REGNUM_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT_00 0x0080
    500 #define SIGNED_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT_00 0
    501 
    502 #define MASK_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT_00 0x0000FF00
    503 #define SHIFT_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT_00 8
    504 #define REGNUM_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT_00 0x0080
    505 #define SIGNED_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT_00 0
    506 
    507 /* Register CR_MMU_TILE_EXT_1 */
    508 #define TOPAZHP_TOP_CR_MMU_TILE_EXT_1 0x0084
    509 #define MASK_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT_01 0x000000FF
    510 #define SHIFT_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT_01 0
    511 #define REGNUM_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT_01 0x0084
    512 #define SIGNED_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT_01 0
    513 
    514 #define MASK_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT_01 0x0000FF00
    515 #define SHIFT_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT_01 8
    516 #define REGNUM_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT_01 0x0084
    517 #define SIGNED_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT_01 0
    518 
    519 /* Register CR_TOPAZHP_CMD_PRIORITY_ENABLE */
    520 #define TOPAZHP_TOP_CR_TOPAZHP_CMD_PRIORITY_ENABLE 0x0090
    521 #define MASK_TOPAZHP_TOP_CR_CMD_PRI_BIF 0x00000001
    522 #define SHIFT_TOPAZHP_TOP_CR_CMD_PRI_BIF 0
    523 #define REGNUM_TOPAZHP_TOP_CR_CMD_PRI_BIF 0x0090
    524 #define SIGNED_TOPAZHP_TOP_CR_CMD_PRI_BIF 0
    525 #define TOPAZHP_TOP_CR_CMD_PRI_BIF_PRI_ENABLE		0x00000001		/* Enable setting of mem_cmd_priority for BIF memory transactions */
    526 #define TOPAZHP_TOP_CR_CMD_PRI_BIF_PRI_DISABLE		0x00000000		/* Disable setting of mem_cmd_priority for BIF memory transactions */
    527 
    528 #define MASK_TOPAZHP_TOP_CR_CMD_PRI_LRITC0 0x00000002
    529 #define SHIFT_TOPAZHP_TOP_CR_CMD_PRI_LRITC0 1
    530 #define REGNUM_TOPAZHP_TOP_CR_CMD_PRI_LRITC0 0x0090
    531 #define SIGNED_TOPAZHP_TOP_CR_CMD_PRI_LRITC0 0
    532 #define TOPAZHP_TOP_CR_CMD_PRI_LRITC0_PRI_ENABLE		0x00000001		/* Enable setting of mem_cmd_priority for LRITC0 memory transactions */
    533 #define TOPAZHP_TOP_CR_CMD_PRI_LRITC0_PRI_DISABLE		0x00000000		/* Disable setting of mem_cmd_priority for LRITC0 memory transactions
    534  */
    535 
    536 #define MASK_TOPAZHP_TOP_CR_CMD_PRI_SEQ0_VLC0_DMAC 0x00000004
    537 #define SHIFT_TOPAZHP_TOP_CR_CMD_PRI_SEQ0_VLC0_DMAC 2
    538 #define REGNUM_TOPAZHP_TOP_CR_CMD_PRI_SEQ0_VLC0_DMAC 0x0090
    539 #define SIGNED_TOPAZHP_TOP_CR_CMD_PRI_SEQ0_VLC0_DMAC 0
    540 #define TOPAZHP_TOP_CR_CMD_PRI_SEQ0_VLC0_DMAC_PRI_ENABLE		0x00000001		/* Enable setting of mem_cmd_priority for SEQ0 / VLC0 / DMAC memory
    541  transactions */
    542 #define TOPAZHP_TOP_CR_CMD_PRI_SEQ0_VLC0_DMAC_PRI_DISABLE		0x00000000		/* Disable setting of mem_cmd_priority for SEQ0 / VLC0 / DMAC
    543  memory transactions */
    544 
    545 #define MASK_TOPAZHP_TOP_CR_CMD_PRI_LRITC1 0x00000008
    546 #define SHIFT_TOPAZHP_TOP_CR_CMD_PRI_LRITC1 3
    547 #define REGNUM_TOPAZHP_TOP_CR_CMD_PRI_LRITC1 0x0090
    548 #define SIGNED_TOPAZHP_TOP_CR_CMD_PRI_LRITC1 0
    549 #define TOPAZHP_TOP_CR_CMD_PRI_LRITC1_PRI_ENABLE		0x00000001		/* Enable setting of mem_cmd_priority for LRITC1 memory transactions */
    550 #define TOPAZHP_TOP_CR_CMD_PRI_LRITC1_PRI_DISABLE		0x00000000		/* Disable setting of mem_cmd_priority for LRITC1 memory transactions
    551  */
    552 
    553 #define MASK_TOPAZHP_TOP_CR_CMD_PRI_SEQ1_VLC1 0x00000010
    554 #define SHIFT_TOPAZHP_TOP_CR_CMD_PRI_SEQ1_VLC1 4
    555 #define REGNUM_TOPAZHP_TOP_CR_CMD_PRI_SEQ1_VLC1 0x0090
    556 #define SIGNED_TOPAZHP_TOP_CR_CMD_PRI_SEQ1_VLC1 0
    557 #define TOPAZHP_TOP_CR_CMD_PRI_SEQ1_VLC1_PRI_ENABLE		0x00000001		/* Enable setting of mem_cmd_priority for SEQ1 / VLC1 memory transactions
    558  */
    559 #define TOPAZHP_TOP_CR_CMD_PRI_SEQ1_VLC1_PRI_DISABLE		0x00000000		/* Disable setting of mem_cmd_priority for SEQ1 / VLC1 memory transactions
    560  */
    561 
    562 #define MASK_TOPAZHP_TOP_CR_CMD_PRI_LRITC2 0x00000020
    563 #define SHIFT_TOPAZHP_TOP_CR_CMD_PRI_LRITC2 5
    564 #define REGNUM_TOPAZHP_TOP_CR_CMD_PRI_LRITC2 0x0090
    565 #define SIGNED_TOPAZHP_TOP_CR_CMD_PRI_LRITC2 0
    566 #define TOPAZHP_TOP_CR_CMD_PRI_LRITC2_PRI_ENABLE		0x00000001		/* Enable setting of mem_cmd_priority for LRITC2 memory transactions */
    567 #define TOPAZHP_TOP_CR_CMD_PRI_LRITC2_PRI_DISABLE		0x00000000		/* Disable setting of mem_cmd_priority for LRITC2 memory transactions
    568  */
    569 
    570 #define MASK_TOPAZHP_TOP_CR_CMD_PRI_SEQ2_VLC2 0x00000040
    571 #define SHIFT_TOPAZHP_TOP_CR_CMD_PRI_SEQ2_VLC2 6
    572 #define REGNUM_TOPAZHP_TOP_CR_CMD_PRI_SEQ2_VLC2 0x0090
    573 #define SIGNED_TOPAZHP_TOP_CR_CMD_PRI_SEQ2_VLC2 0
    574 #define TOPAZHP_TOP_CR_CMD_PRI_SEQ2_VLC2_PRI_ENABLE		0x00000001		/* Enable setting of mem_cmd_priority for SEQ2 / VLC2 memory transactions
    575  */
    576 #define TOPAZHP_TOP_CR_CMD_PRI_SEQ2_VLC2_PRI_DISABLE		0x00000000		/* Disable setting of mem_cmd_priority for SEQ2 / VLC2 memory transactions
    577  */
    578 
    579 /* Register CR_TOPAZHP_LIMITED_THROUGHPUT */
    580 #define TOPAZHP_TOP_CR_TOPAZHP_LIMITED_THROUGHPUT 0x0094
    581 #define MASK_TOPAZHP_TOP_CR_LIMITED_WORDS 0x000003FF
    582 #define SHIFT_TOPAZHP_TOP_CR_LIMITED_WORDS 0
    583 #define REGNUM_TOPAZHP_TOP_CR_LIMITED_WORDS 0x0094
    584 #define SIGNED_TOPAZHP_TOP_CR_LIMITED_WORDS 0
    585 
    586 #define MASK_TOPAZHP_TOP_CR_REQUEST_GAP 0x0FFF0000
    587 #define SHIFT_TOPAZHP_TOP_CR_REQUEST_GAP 16
    588 #define REGNUM_TOPAZHP_TOP_CR_REQUEST_GAP 0x0094
    589 #define SIGNED_TOPAZHP_TOP_CR_REQUEST_GAP 0
    590 
    591 /* Register CR_FIRMWARE_REG_1 */
    592 #define TOPAZHP_TOP_CR_FIRMWARE_REG_1 0x0100
    593 #define MASK_TOPAZHP_TOP_CR_FIRMWARE_REG_1 0xFFFFFFFF
    594 #define SHIFT_TOPAZHP_TOP_CR_FIRMWARE_REG_1 0
    595 #define REGNUM_TOPAZHP_TOP_CR_FIRMWARE_REG_1 0x0100
    596 #define SIGNED_TOPAZHP_TOP_CR_FIRMWARE_REG_1 0
    597 
    598 /* Register CR_FIRMWARE_REG_2 */
    599 #define TOPAZHP_TOP_CR_FIRMWARE_REG_2 0x0104
    600 #define MASK_TOPAZHP_TOP_CR_FIRMWARE_REG_2 0xFFFFFFFF
    601 #define SHIFT_TOPAZHP_TOP_CR_FIRMWARE_REG_2 0
    602 #define REGNUM_TOPAZHP_TOP_CR_FIRMWARE_REG_2 0x0104
    603 #define SIGNED_TOPAZHP_TOP_CR_FIRMWARE_REG_2 0
    604 
    605 /* Register CR_FIRMWARE_REG_3 */
    606 #define TOPAZHP_TOP_CR_FIRMWARE_REG_3 0x0108
    607 #define MASK_TOPAZHP_TOP_CR_FIRMWARE_REG_3 0xFFFFFFFF
    608 #define SHIFT_TOPAZHP_TOP_CR_FIRMWARE_REG_3 0
    609 #define REGNUM_TOPAZHP_TOP_CR_FIRMWARE_REG_3 0x0108
    610 #define SIGNED_TOPAZHP_TOP_CR_FIRMWARE_REG_3 0
    611 
    612 /* Register CR_CYCLE_COUNTER */
    613 #define TOPAZHP_TOP_CR_CYCLE_COUNTER 0x0110
    614 #define MASK_TOPAZHP_TOP_CR_CYCLE_COUNTER 0xFFFFFFFF
    615 #define SHIFT_TOPAZHP_TOP_CR_CYCLE_COUNTER 0
    616 #define REGNUM_TOPAZHP_TOP_CR_CYCLE_COUNTER 0x0110
    617 #define SIGNED_TOPAZHP_TOP_CR_CYCLE_COUNTER 0
    618 
    619 /* Register CR_CYCLE_COUNTER_CTRL */
    620 #define TOPAZHP_TOP_CR_CYCLE_COUNTER_CTRL 0x0114
    621 #define MASK_TOPAZHP_TOP_CR_CYCLE_COUNTER_ENABLE 0x00000001
    622 #define SHIFT_TOPAZHP_TOP_CR_CYCLE_COUNTER_ENABLE 0
    623 #define REGNUM_TOPAZHP_TOP_CR_CYCLE_COUNTER_ENABLE 0x0114
    624 #define SIGNED_TOPAZHP_TOP_CR_CYCLE_COUNTER_ENABLE 0
    625 
    626 /* Register CR_MULTICORE_IDLE_PWR_MAN */
    627 #define TOPAZHP_TOP_CR_MULTICORE_IDLE_PWR_MAN 0x0118
    628 #define MASK_TOPAZHP_TOP_CR_TOPAZ_IDLE_DISABLE 0x00000001
    629 #define SHIFT_TOPAZHP_TOP_CR_TOPAZ_IDLE_DISABLE 0
    630 #define REGNUM_TOPAZHP_TOP_CR_TOPAZ_IDLE_DISABLE 0x0118
    631 #define SIGNED_TOPAZHP_TOP_CR_TOPAZ_IDLE_DISABLE 0
    632 
    633 /* Register CR_DIRECT_BIAS_TABLE */
    634 #define TOPAZHP_TOP_CR_DIRECT_BIAS_TABLE 0x0124
    635 #define MASK_TOPAZHP_TOP_CR_DIRECT_BIAS_TABLE 0x00007FFF
    636 #define SHIFT_TOPAZHP_TOP_CR_DIRECT_BIAS_TABLE 0
    637 #define REGNUM_TOPAZHP_TOP_CR_DIRECT_BIAS_TABLE 0x0124
    638 #define SIGNED_TOPAZHP_TOP_CR_DIRECT_BIAS_TABLE 0
    639 
    640 /* Register CR_INTRA_BIAS_TABLE */
    641 #define TOPAZHP_TOP_CR_INTRA_BIAS_TABLE 0x0128
    642 #define MASK_TOPAZHP_TOP_CR_INTRA8_BIAS_TABLE 0xFFFF0000
    643 #define SHIFT_TOPAZHP_TOP_CR_INTRA8_BIAS_TABLE 16
    644 #define REGNUM_TOPAZHP_TOP_CR_INTRA8_BIAS_TABLE 0x0128
    645 #define SIGNED_TOPAZHP_TOP_CR_INTRA8_BIAS_TABLE 0
    646 
    647 #define MASK_TOPAZHP_TOP_CR_INTRA16_BIAS_TABLE 0x0000FFFF
    648 #define SHIFT_TOPAZHP_TOP_CR_INTRA16_BIAS_TABLE 0
    649 #define REGNUM_TOPAZHP_TOP_CR_INTRA16_BIAS_TABLE 0x0128
    650 #define SIGNED_TOPAZHP_TOP_CR_INTRA16_BIAS_TABLE 0
    651 
    652 /* Register CR_INTER_BIAS_TABLE */
    653 #define TOPAZHP_TOP_CR_INTER_BIAS_TABLE 0x012C
    654 #define MASK_TOPAZHP_TOP_CR_INTER_BIAS_TABLE 0x0000FFFF
    655 #define SHIFT_TOPAZHP_TOP_CR_INTER_BIAS_TABLE 0
    656 #define REGNUM_TOPAZHP_TOP_CR_INTER_BIAS_TABLE 0x012C
    657 #define SIGNED_TOPAZHP_TOP_CR_INTER_BIAS_TABLE 0
    658 
    659 /* Register CR_INTRA_SCALE_TABLE */
    660 #define TOPAZHP_TOP_CR_INTRA_SCALE_TABLE 0x0130
    661 #define MASK_TOPAZHP_TOP_CR_INTRA8_SCALE_TABLE 0x00000007
    662 #define SHIFT_TOPAZHP_TOP_CR_INTRA8_SCALE_TABLE 0
    663 #define REGNUM_TOPAZHP_TOP_CR_INTRA8_SCALE_TABLE 0x0130
    664 #define SIGNED_TOPAZHP_TOP_CR_INTRA8_SCALE_TABLE 0
    665 
    666 /* Register CR_QPCB_QPCR_OFFSET */
    667 #define TOPAZHP_TOP_CR_QPCB_QPCR_OFFSET 0x0134
    668 #define MASK_TOPAZHP_TOP_CR_QPCB_OFFSET 0x0000001F
    669 #define SHIFT_TOPAZHP_TOP_CR_QPCB_OFFSET 0
    670 #define REGNUM_TOPAZHP_TOP_CR_QPCB_OFFSET 0x0134
    671 #define SIGNED_TOPAZHP_TOP_CR_QPCB_OFFSET 0
    672 
    673 #define MASK_TOPAZHP_TOP_CR_QPCR_OFFSET 0x00001F00
    674 #define SHIFT_TOPAZHP_TOP_CR_QPCR_OFFSET 8
    675 #define REGNUM_TOPAZHP_TOP_CR_QPCR_OFFSET 0x0134
    676 #define SIGNED_TOPAZHP_TOP_CR_QPCR_OFFSET 0
    677 
    678 /* Register CR_INTER_INTRA_SCALE_TABLE */
    679 #define TOPAZHP_TOP_CR_INTER_INTRA_SCALE_TABLE 0x0140
    680 #define MASK_TOPAZHP_TOP_CR_INTRA_SCALING_TABLE 0x0000FF00
    681 #define SHIFT_TOPAZHP_TOP_CR_INTRA_SCALING_TABLE 8
    682 #define REGNUM_TOPAZHP_TOP_CR_INTRA_SCALING_TABLE 0x0140
    683 #define SIGNED_TOPAZHP_TOP_CR_INTRA_SCALING_TABLE 0
    684 
    685 #define MASK_TOPAZHP_TOP_CR_INTER_SCALING_TABLE 0x000000FF
    686 #define SHIFT_TOPAZHP_TOP_CR_INTER_SCALING_TABLE 0
    687 #define REGNUM_TOPAZHP_TOP_CR_INTER_SCALING_TABLE 0x0140
    688 #define SIGNED_TOPAZHP_TOP_CR_INTER_SCALING_TABLE 0
    689 
    690 /* Register CR_SKIPPED_CODED_SCALE_TABLE */
    691 #define TOPAZHP_TOP_CR_SKIPPED_CODED_SCALE_TABLE 0x0144
    692 #define MASK_TOPAZHP_TOP_CR_CODED_SCALING_TABLE 0x0000FF00
    693 #define SHIFT_TOPAZHP_TOP_CR_CODED_SCALING_TABLE 8
    694 #define REGNUM_TOPAZHP_TOP_CR_CODED_SCALING_TABLE 0x0144
    695 #define SIGNED_TOPAZHP_TOP_CR_CODED_SCALING_TABLE 0
    696 
    697 #define MASK_TOPAZHP_TOP_CR_SKIPPED_SCALING_TABLE 0x000000FF
    698 #define SHIFT_TOPAZHP_TOP_CR_SKIPPED_SCALING_TABLE 0
    699 #define REGNUM_TOPAZHP_TOP_CR_SKIPPED_SCALING_TABLE 0x0144
    700 #define SIGNED_TOPAZHP_TOP_CR_SKIPPED_SCALING_TABLE 0
    701 
    702 /* Register CR_POLYNOM_ALPHA_COEFF_CORE_0 */
    703 #define TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_0 0x0148
    704 #define MASK_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_00 0x000000FF
    705 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_00 0
    706 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_00 0x0148
    707 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_00 0
    708 
    709 #define MASK_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_00 0x007FFF00
    710 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_00 8
    711 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_00 0x0148
    712 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_00 1
    713 
    714 /* Register CR_POLYNOM_GAMMA_COEFF_CORE_0 */
    715 #define TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_0 0x014C
    716 #define MASK_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_00 0x0003FFFF
    717 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_00 0
    718 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_00 0x014C
    719 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_00 0
    720 
    721 /* Register CR_POLYNOM_CUTOFF_CORE_0 */
    722 #define TOPAZHP_TOP_CR_POLYNOM_CUTOFF_CORE_0 0x0150
    723 #define MASK_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_00 0x0000003F
    724 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_00 0
    725 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_00 0x0150
    726 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_00 0
    727 
    728 #define MASK_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_00 0x00000FC0
    729 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_00 6
    730 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_00 0x0150
    731 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_00 0
    732 
    733 /* Register CR_POLYNOM_ALPHA_COEFF_CORE_1 */
    734 #define TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_1 0x0154
    735 #define MASK_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_01 0x000000FF
    736 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_01 0
    737 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_01 0x0154
    738 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_01 0
    739 
    740 #define MASK_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_01 0x007FFF00
    741 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_01 8
    742 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_01 0x0154
    743 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_01 1
    744 
    745 /* Register CR_POLYNOM_GAMMA_COEFF_CORE_1 */
    746 #define TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_1 0x0158
    747 #define MASK_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_01 0x0003FFFF
    748 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_01 0
    749 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_01 0x0158
    750 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_01 0
    751 
    752 /* Register CR_POLYNOM_CUTOFF_CORE_1 */
    753 #define TOPAZHP_TOP_CR_POLYNOM_CUTOFF_CORE_1 0x015C
    754 #define MASK_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_01 0x0000003F
    755 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_01 0
    756 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_01 0x015C
    757 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_01 0
    758 
    759 #define MASK_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_01 0x00000FC0
    760 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_01 6
    761 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_01 0x015C
    762 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_01 0
    763 
    764 /* Register CR_POLYNOM_ALPHA_COEFF_CORE_2 */
    765 #define TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_2 0x0160
    766 #define MASK_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_02 0x000000FF
    767 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_02 0
    768 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_02 0x0160
    769 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE_02 0
    770 
    771 #define MASK_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_02 0x007FFF00
    772 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_02 8
    773 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_02 0x0160
    774 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE_02 1
    775 
    776 /* Register CR_POLYNOM_GAMMA_COEFF_CORE_2 */
    777 #define TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_2 0x0164
    778 #define MASK_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_02 0x0003FFFF
    779 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_02 0
    780 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_02 0x0164
    781 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE_02 0
    782 
    783 /* Register CR_POLYNOM_CUTOFF_CORE_2 */
    784 #define TOPAZHP_TOP_CR_POLYNOM_CUTOFF_CORE_2 0x0168
    785 #define MASK_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_02 0x0000003F
    786 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_02 0
    787 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_02 0x0168
    788 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE_02 0
    789 
    790 #define MASK_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_02 0x00000FC0
    791 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_02 6
    792 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_02 0x0168
    793 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE_02 0
    794 
    795 /* Register CR_FIRMWARE_REG_4 */
    796 #define TOPAZHP_TOP_CR_FIRMWARE_REG_4 0x0300
    797 #define MASK_TOPAZHP_TOP_CR_FIRMWARE_REG_4 0xFFFFFFFF
    798 #define SHIFT_TOPAZHP_TOP_CR_FIRMWARE_REG_4 0
    799 #define REGNUM_TOPAZHP_TOP_CR_FIRMWARE_REG_4 0x0300
    800 #define SIGNED_TOPAZHP_TOP_CR_FIRMWARE_REG_4 0
    801 
    802 /* Register CR_FIRMWARE_REG_5 */
    803 #define TOPAZHP_TOP_CR_FIRMWARE_REG_5 0x0304
    804 #define MASK_TOPAZHP_TOP_CR_FIRMWARE_REG_5 0xFFFFFFFF
    805 #define SHIFT_TOPAZHP_TOP_CR_FIRMWARE_REG_5 0
    806 #define REGNUM_TOPAZHP_TOP_CR_FIRMWARE_REG_5 0x0304
    807 #define SIGNED_TOPAZHP_TOP_CR_FIRMWARE_REG_5 0
    808 
    809 /* Register CR_FIRMWARE_REG_6 */
    810 #define TOPAZHP_TOP_CR_FIRMWARE_REG_6 0x0308
    811 #define MASK_TOPAZHP_TOP_CR_FIRMWARE_REG_6 0xFFFFFFFF
    812 #define SHIFT_TOPAZHP_TOP_CR_FIRMWARE_REG_6 0
    813 #define REGNUM_TOPAZHP_TOP_CR_FIRMWARE_REG_6 0x0308
    814 #define SIGNED_TOPAZHP_TOP_CR_FIRMWARE_REG_6 0
    815 
    816 /* Register CR_FIRMWARE_REG_7 */
    817 #define TOPAZHP_TOP_CR_FIRMWARE_REG_7 0x030C
    818 #define MASK_TOPAZHP_TOP_CR_FIRMWARE_REG_7 0xFFFFFFFF
    819 #define SHIFT_TOPAZHP_TOP_CR_FIRMWARE_REG_7 0
    820 #define REGNUM_TOPAZHP_TOP_CR_FIRMWARE_REG_7 0x030C
    821 #define SIGNED_TOPAZHP_TOP_CR_FIRMWARE_REG_7 0
    822 
    823 /* Register CR_MULTICORE_RSVD0 */
    824 #define TOPAZHP_TOP_CR_MULTICORE_RSVD0 0x03B0
    825 #define MASK_TOPAZHP_TOP_CR_RESERVED0 0x000000FF
    826 #define SHIFT_TOPAZHP_TOP_CR_RESERVED0 0
    827 #define REGNUM_TOPAZHP_TOP_CR_RESERVED0 0x03B0
    828 #define SIGNED_TOPAZHP_TOP_CR_RESERVED0 0
    829 
    830 /* Register CR_TOPAZHP_CORE_ID */
    831 #define TOPAZHP_TOP_CR_TOPAZHP_CORE_ID 0x03C0
    832 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_CORE_CONFIG 0x0000FFFF
    833 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_CORE_CONFIG 0
    834 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_CORE_CONFIG 0x03C0
    835 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_CORE_CONFIG 0
    836 
    837 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_CORE_ID 0x00FF0000
    838 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_CORE_ID 16
    839 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_CORE_ID 0x03C0
    840 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_CORE_ID 0
    841 
    842 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_GROUP_ID 0xFF000000
    843 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_GROUP_ID 24
    844 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_GROUP_ID 0x03C0
    845 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_GROUP_ID 0
    846 
    847 /* Register CR_TOPAZHP_CORE_REV */
    848 #define TOPAZHP_TOP_CR_TOPAZHP_CORE_REV 0x03D0
    849 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_MAINT_REV 0x000000FF
    850 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_MAINT_REV 0
    851 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_MAINT_REV 0x03D0
    852 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_MAINT_REV 0
    853 
    854 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_MINOR_REV 0x0000FF00
    855 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_MINOR_REV 8
    856 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_MINOR_REV 0x03D0
    857 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_MINOR_REV 0
    858 
    859 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_MAJOR_REV 0x00FF0000
    860 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_MAJOR_REV 16
    861 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_MAJOR_REV 0x03D0
    862 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_MAJOR_REV 0
    863 
    864 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_DESIGNER 0xFF000000
    865 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_DESIGNER 24
    866 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_DESIGNER 0x03D0
    867 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_DESIGNER 0
    868 
    869 /* Register CR_TOPAZHP_CORE_DES1 */
    870 #define TOPAZHP_TOP_CR_TOPAZHP_CORE_DES1 0x03E0
    871 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_SCALER_SUPPORTED 0x00000080
    872 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_SCALER_SUPPORTED 7
    873 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_SCALER_SUPPORTED 0x03E0
    874 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_SCALER_SUPPORTED 0
    875 
    876 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_GENERATE_PERFORMANCE_STORE 0x00000100
    877 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_GENERATE_PERFORMANCE_STORE 8
    878 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_GENERATE_PERFORMANCE_STORE 0x03E0
    879 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_GENERATE_PERFORMANCE_STORE 0
    880 
    881 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_LOSSLESS_SUPPORTED 0x00000200
    882 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_LOSSLESS_SUPPORTED 9
    883 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_LOSSLESS_SUPPORTED 0x03E0
    884 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_LOSSLESS_SUPPORTED 0
    885 
    886 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_CUSTOM_QUANT_SUPPORTED 0x00000400
    887 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_CUSTOM_QUANT_SUPPORTED 10
    888 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_CUSTOM_QUANT_SUPPORTED 0x03E0
    889 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_CUSTOM_QUANT_SUPPORTED 0
    890 
    891 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_MPEG2_SUPPORTED 0x00000800
    892 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_MPEG2_SUPPORTED 11
    893 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_MPEG2_SUPPORTED 0x03E0
    894 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_MPEG2_SUPPORTED 0
    895 
    896 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_SIGNATURES_SUPPORTED_SUBSET 0x00001000
    897 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_SIGNATURES_SUPPORTED_SUBSET 12
    898 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_SIGNATURES_SUPPORTED_SUBSET 0x03E0
    899 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_SIGNATURES_SUPPORTED_SUBSET 0
    900 
    901 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_SIGNATURES_SUPPORTED_ALL 0x00002000
    902 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_SIGNATURES_SUPPORTED_ALL 13
    903 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_SIGNATURES_SUPPORTED_ALL 0x03E0
    904 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_SIGNATURES_SUPPORTED_ALL 0
    905 
    906 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_WEIGHTED_PRED_ME_SUPPORTED 0x00004000
    907 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_WEIGHTED_PRED_ME_SUPPORTED 14
    908 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_WEIGHTED_PRED_ME_SUPPORTED 0x03E0
    909 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_WEIGHTED_PRED_ME_SUPPORTED 0
    910 
    911 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_WEIGHTED_PRED_SUPPORTED 0x00008000
    912 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_WEIGHTED_PRED_SUPPORTED 15
    913 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_WEIGHTED_PRED_SUPPORTED 0x03E0
    914 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_WEIGHTED_PRED_SUPPORTED 0
    915 
    916 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_2_REF_ON_P_PIC_SUPPORTED 0x00010000
    917 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_2_REF_ON_P_PIC_SUPPORTED 16
    918 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_2_REF_ON_P_PIC_SUPPORTED 0x03E0
    919 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_2_REF_ON_P_PIC_SUPPORTED 0
    920 
    921 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_SPATIAL_DIRECT_SUPPORTED 0x00020000
    922 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_SPATIAL_DIRECT_SUPPORTED 17
    923 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_SPATIAL_DIRECT_SUPPORTED 0x03E0
    924 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_SPATIAL_DIRECT_SUPPORTED 0
    925 
    926 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_MULTIPASS_SUPPORTED 0x00040000
    927 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_MULTIPASS_SUPPORTED 18
    928 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_MULTIPASS_SUPPORTED 0x03E0
    929 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_MULTIPASS_SUPPORTED 0
    930 
    931 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_DEFAULT_TABLES_SUPPORTED 0x00080000
    932 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_DEFAULT_TABLES_SUPPORTED 19
    933 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_DEFAULT_TABLES_SUPPORTED 0x03E0
    934 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_DEFAULT_TABLES_SUPPORTED 0
    935 
    936 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_8X8_TRANSFORM_SUPPORTED 0x00100000
    937 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_8X8_TRANSFORM_SUPPORTED 20
    938 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_8X8_TRANSFORM_SUPPORTED 0x03E0
    939 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_8X8_TRANSFORM_SUPPORTED 0
    940 
    941 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_INTERLACED_SUPPORTED 0x00200000
    942 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_INTERLACED_SUPPORTED 21
    943 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_INTERLACED_SUPPORTED 0x03E0
    944 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_INTERLACED_SUPPORTED 0
    945 
    946 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_B_PIC_SUPPORTED 0x00400000
    947 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_B_PIC_SUPPORTED 22
    948 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_B_PIC_SUPPORTED 0x03E0
    949 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_B_PIC_SUPPORTED 0
    950 
    951 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_16X8_8X16_SUPPORTED 0x00800000
    952 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_16X8_8X16_SUPPORTED 23
    953 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_16X8_8X16_SUPPORTED 0x03E0
    954 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_16X8_8X16_SUPPORTED 0
    955 
    956 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_CABAC_SUPPORTED 0x01000000
    957 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_CABAC_SUPPORTED 24
    958 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_CABAC_SUPPORTED 0x03E0
    959 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_CABAC_SUPPORTED 0
    960 
    961 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_SLAVE_JPEG_SUPPORTED 0x02000000
    962 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_SLAVE_JPEG_SUPPORTED 25
    963 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_SLAVE_JPEG_SUPPORTED 0x03E0
    964 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_SLAVE_JPEG_SUPPORTED 0
    965 
    966 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_JPEG_SUPPORTED 0x04000000
    967 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_JPEG_SUPPORTED 26
    968 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_JPEG_SUPPORTED 0x03E0
    969 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_JPEG_SUPPORTED 0
    970 
    971 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H263_SUPPORTED 0x08000000
    972 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H263_SUPPORTED 27
    973 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H263_SUPPORTED 0x03E0
    974 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H263_SUPPORTED 0
    975 
    976 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_MPEG4_SUPPORTED 0x10000000
    977 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_MPEG4_SUPPORTED 28
    978 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_MPEG4_SUPPORTED 0x03E0
    979 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_MPEG4_SUPPORTED 0
    980 
    981 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_H264_SUPPORTED 0x20000000
    982 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_H264_SUPPORTED 29
    983 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_H264_SUPPORTED 0x03E0
    984 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_H264_SUPPORTED 0
    985 
    986 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_DMAC_SUPPORTED 0x40000000
    987 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_DMAC_SUPPORTED 30
    988 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_DMAC_SUPPORTED 0x03E0
    989 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_DMAC_SUPPORTED 0
    990 
    991 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_MMU_SUPPORTED 0x80000000
    992 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_MMU_SUPPORTED 31
    993 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_MMU_SUPPORTED 0x03E0
    994 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_MMU_SUPPORTED 0
    995 
    996 /* Register CR_TOPAZHP_CORE_DES2 */
    997 #define TOPAZHP_TOP_CR_TOPAZHP_CORE_DES2 0x03F0
    998 #define MASK_TOPAZHP_TOP_CR_TOPAZHP_DESIGNER2 0xFFFFFFFF
    999 #define SHIFT_TOPAZHP_TOP_CR_TOPAZHP_DESIGNER2 0
   1000 #define REGNUM_TOPAZHP_TOP_CR_TOPAZHP_DESIGNER2 0x03F0
   1001 #define SIGNED_TOPAZHP_TOP_CR_TOPAZHP_DESIGNER2 0
   1002 
   1003 
   1004 /* Table MMU_DIR_LIST_BASE */
   1005 
   1006 /* Register CR_MMU_DIR_LIST_BASE */
   1007 #define TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE(X) (0x0030 + (4 * (X)))
   1008 #define MASK_TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE_ADDR 0xFFFFFFF0
   1009 #define SHIFT_TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE_ADDR 4
   1010 #define REGNUM_TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE_ADDR 0x0030
   1011 #define SIGNED_TOPAZHP_TOP_CR_MMU_DIR_LIST_BASE_ADDR 0
   1012 
   1013 /* Number of entries in table MMU_DIR_LIST_BASE */
   1014 
   1015 #define TOPAZHP_TOP_MMU_DIR_LIST_BASE_SIZE_UINT32 1
   1016 #define TOPAZHP_TOP_MMU_DIR_LIST_BASE_NUM_ENTRIES 1
   1017 
   1018 
   1019 /* Table MMU_TILE */
   1020 
   1021 /* Register CR_MMU_TILE */
   1022 #define TOPAZHP_TOP_CR_MMU_TILE(X)  (0x0038 + (4 * (X)))
   1023 #define MASK_TOPAZHP_TOP_CR_TILE_MIN_ADDR 0x00000FFF
   1024 #define SHIFT_TOPAZHP_TOP_CR_TILE_MIN_ADDR 0
   1025 #define REGNUM_TOPAZHP_TOP_CR_TILE_MIN_ADDR 0x0038
   1026 #define SIGNED_TOPAZHP_TOP_CR_TILE_MIN_ADDR 0
   1027 
   1028 #define MASK_TOPAZHP_TOP_CR_TILE_MAX_ADDR 0x00FFF000
   1029 #define SHIFT_TOPAZHP_TOP_CR_TILE_MAX_ADDR 12
   1030 #define REGNUM_TOPAZHP_TOP_CR_TILE_MAX_ADDR 0x0038
   1031 #define SIGNED_TOPAZHP_TOP_CR_TILE_MAX_ADDR 0
   1032 
   1033 #define MASK_TOPAZHP_TOP_CR_TILE_STRIDE 0x07000000
   1034 #define SHIFT_TOPAZHP_TOP_CR_TILE_STRIDE 24
   1035 #define REGNUM_TOPAZHP_TOP_CR_TILE_STRIDE 0x0038
   1036 #define SIGNED_TOPAZHP_TOP_CR_TILE_STRIDE 0
   1037 
   1038 #define MASK_TOPAZHP_TOP_CR_TILE_ENABLE 0x10000000
   1039 #define SHIFT_TOPAZHP_TOP_CR_TILE_ENABLE 28
   1040 #define REGNUM_TOPAZHP_TOP_CR_TILE_ENABLE 0x0038
   1041 #define SIGNED_TOPAZHP_TOP_CR_TILE_ENABLE 0
   1042 
   1043 /* Number of entries in table MMU_TILE */
   1044 
   1045 #define TOPAZHP_TOP_MMU_TILE_SIZE_UINT32 2
   1046 #define TOPAZHP_TOP_MMU_TILE_NUM_ENTRIES 2
   1047 
   1048 
   1049 /* Table MMU_TILE_EXT */
   1050 
   1051 /* Register CR_MMU_TILE_EXT */
   1052 #define TOPAZHP_TOP_CR_MMU_TILE_EXT(X) (0x0080 + (4 * (X)))
   1053 #define MASK_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT 0x000000FF
   1054 #define SHIFT_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT 0
   1055 #define REGNUM_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT 0x0080
   1056 #define SIGNED_TOPAZHP_TOP_CR_TILE_MIN_ADDR_EXT 0
   1057 
   1058 #define MASK_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT 0x0000FF00
   1059 #define SHIFT_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT 8
   1060 #define REGNUM_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT 0x0080
   1061 #define SIGNED_TOPAZHP_TOP_CR_TILE_MAX_ADDR_EXT 0
   1062 
   1063 /* Number of entries in table MMU_TILE_EXT */
   1064 
   1065 #define TOPAZHP_TOP_MMU_TILE_EXT_SIZE_UINT32 2
   1066 #define TOPAZHP_TOP_MMU_TILE_EXT_NUM_ENTRIES 2
   1067 
   1068 
   1069 /* Table TABLES_POLYNOM_TABLE */
   1070 
   1071 /* Register CR_POLYNOM_ALPHA_COEFF_CORE */
   1072 #define TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE(X) (0x0148 + (12 * (X)))
   1073 #define MASK_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE 0x000000FF
   1074 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE 0
   1075 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE 0x0148
   1076 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_ALPHA_COEFF_CORE 0
   1077 
   1078 #define MASK_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE 0x007FFF00
   1079 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE 8
   1080 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE 0x0148
   1081 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_BETA_COEFF_CORE 1
   1082 
   1083 /* Register CR_POLYNOM_GAMMA_COEFF_CORE */
   1084 #define TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE(X) (0x014C + (12 * (X)))
   1085 #define MASK_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE 0x0003FFFF
   1086 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE 0
   1087 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE 0x014C
   1088 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_GAMMA_COEFF_CORE 0
   1089 
   1090 /* Register CR_POLYNOM_CUTOFF_CORE */
   1091 #define TOPAZHP_TOP_CR_POLYNOM_CUTOFF_CORE(X) (0x0150 + (12 * (X)))
   1092 #define MASK_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE 0x0000003F
   1093 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE 0
   1094 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE 0x0150
   1095 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_SAD_CUTOFF_CORE 0
   1096 
   1097 #define MASK_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE 0x00000FC0
   1098 #define SHIFT_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE 6
   1099 #define REGNUM_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE 0x0150
   1100 #define SIGNED_TOPAZHP_TOP_CR_POLYNOM_SATD_CUTOFF_CORE 0
   1101 
   1102 /* Number of entries in table TABLES_POLYNOM_TABLE */
   1103 
   1104 #define TOPAZHP_TOP_TABLES_POLYNOM_TABLE_SIZE_UINT32 9
   1105 #define TOPAZHP_TOP_TABLES_POLYNOM_TABLE_NUM_ENTRIES 3
   1106 
   1107 /*
   1108 	Byte range covering the group TOPAZHP_MULTICORE file
   1109 */
   1110 
   1111 #define TOPAZHP_TOP_TOPAZHP_MULTICORE_REGISTERS_START		0x00000000
   1112 #define TOPAZHP_TOP_TOPAZHP_MULTICORE_REGISTERS_END  		0x000003F3
   1113 
   1114 /*
   1115 	Byte range covering the whole register file
   1116 */
   1117 
   1118 #define TOPAZHP_TOP_REGISTERS_START		0x00000000
   1119 #define TOPAZHP_TOP_REGISTERS_END  		0x000003F3
   1120 #define TOPAZHP_TOP_REG_DEFAULT_TABLE struct {\
   1121 			IMG_UINT16 uRegOffset;\
   1122 			IMG_UINT32 uRegDefault;\
   1123 			IMG_UINT32 uRegMask;\
   1124 			bool bReadonly;\
   1125 			const char* pszName;\
   1126 		} TOPAZHP_TOP_Defaults[] = {\
   1127 	{0x0000, 0x00000000, 0x00000007, 0, "CR_MULTICORE_SRST" } ,\
   1128 	{0x0004, 0x00000000, 0xC0FFFF0F, 0, "CR_MULTICORE_INT_STAT" } ,\
   1129 	{0x0008, 0x00000000, 0x40FFFF0F, 0, "CR_MULTICORE_MTX_INT_ENAB" } ,\
   1130 	{0x000C, 0x00000000, 0x80FFFF0F, 0, "CR_MULTICORE_HOST_INT_ENAB" } ,\
   1131 	{0x0010, 0x00000000, 0x0000000F, 0, "CR_MULTICORE_INT_CLEAR" } ,\
   1132 	{0x0014, 0x00000000, 0x00000002, 0, "CR_MULTICORE_MAN_CLK_GATE" } ,\
   1133 	{0x0018, 0x00000000, 0x00000003, 0, "CR_TOPAZ_MTX_C_RATIO" } ,\
   1134 	{0x001C, 0x00000000, 0xFFFFF001, 1, "CR_MMU_STATUS" } ,\
   1135 	{0x0020, 0x00000000, 0x000000FF, 1, "CR_MMU_MEM_REQ" } ,\
   1136 	{0x0024, 0x00010000, 0x0001070F, 0, "CR_MMU_CONTROL0" } ,\
   1137 	{0x0028, 0xC000000C, 0xFFFFFFFF, 0, "CR_MMU_CONTROL1" } ,\
   1138 	{0x002C, 0x00000000, 0x00000009, 0, "CR_MMU_CONTROL2" } ,\
   1139 	{0x0030, 0x00000000, 0xFFFFFFF0, 0, "CR_MMU_DIR_LIST_BASE_0" } ,\
   1140 	{0x0038, 0x00000000, 0x17FFFFFF, 0, "CR_MMU_TILE_0" } ,\
   1141 	{0x003C, 0x00000000, 0x17FFFFFF, 0, "CR_MMU_TILE_1" } ,\
   1142 	{0x0044, 0x00010004, 0x0F0F0F1F, 0, "CR_MTX_DEBUG_MSTR" } ,\
   1143 	{0x0048, 0x00000000, 0x0F0F0F1F, 0, "CR_MTX_DEBUG_SLV" } ,\
   1144 	{0x0050, 0x00000000, 0xC0000007, 0, "CR_MULTICORE_CORE_SEL_0" } ,\
   1145 	{0x0054, 0x00000000, 0x0000001F, 0, "CR_MULTICORE_CORE_SEL_1" } ,\
   1146 	{0x0058, 0x08020102, 0x0F07071F, 1, "CR_MULTICORE_HW_CFG" } ,\
   1147 	{0x0060, 0x00000000, 0xFFFFFFFF, 0, "CR_MULTICORE_CMD_FIFO_WRITE" } ,\
   1148 	{0x0064, 0x00000020, 0x000001FF, 1, "CR_MULTICORE_CMD_FIFO_WRITE_SPACE" } ,\
   1149 	{0x0070, 0x00000000, 0xFFFFFFFF, 0, "CR_TOPAZ_CMD_FIFO_READ" } ,\
   1150 	{0x0074, 0x00000000, 0x000001FF, 1, "CR_TOPAZ_CMD_FIFO_READ_AVAILABLE" } ,\
   1151 	{0x0078, 0x00000000, 0x00000001, 0, "CR_TOPAZ_CMD_FIFO_FLUSH" } ,\
   1152 	{0x0080, 0x00000000, 0x0000FFFF, 0, "CR_MMU_TILE_EXT_0" } ,\
   1153 	{0x0084, 0x00000000, 0x0000FFFF, 0, "CR_MMU_TILE_EXT_1" } ,\
   1154 	{0x0090, 0x00000001, 0x0000007F, 0, "CR_TOPAZHP_CMD_PRIORITY_ENABLE" } ,\
   1155 	{0x0094, 0x00000000, 0x0FFF03FF, 0, "CR_TOPAZHP_LIMITED_THROUGHPUT" } ,\
   1156 	{0x0100, 0x00000000, 0xFFFFFFFF, 0, "CR_FIRMWARE_REG_1" } ,\
   1157 	{0x0104, 0x00000000, 0xFFFFFFFF, 0, "CR_FIRMWARE_REG_2" } ,\
   1158 	{0x0108, 0x00000000, 0xFFFFFFFF, 0, "CR_FIRMWARE_REG_3" } ,\
   1159 	{0x0110, 0x00000000, 0xFFFFFFFF, 0, "CR_CYCLE_COUNTER" } ,\
   1160 	{0x0114, 0x00000000, 0x00000001, 0, "CR_CYCLE_COUNTER_CTRL" } ,\
   1161 	{0x0118, 0x00000000, 0x00000001, 0, "CR_MULTICORE_IDLE_PWR_MAN" } ,\
   1162 	{0x0124, 0x00000000, 0x00007FFF, 0, "CR_DIRECT_BIAS_TABLE" } ,\
   1163 	{0x0128, 0x00000000, 0xFFFFFFFF, 0, "CR_INTRA_BIAS_TABLE" } ,\
   1164 	{0x012C, 0x00000000, 0x0000FFFF, 0, "CR_INTER_BIAS_TABLE" } ,\
   1165 	{0x0130, 0x00000000, 0x00000007, 0, "CR_INTRA_SCALE_TABLE" } ,\
   1166 	{0x0134, 0x00000000, 0x00001F1F, 0, "CR_QPCB_QPCR_OFFSET" } ,\
   1167 	{0x0140, 0x00000000, 0x0000FFFF, 0, "CR_INTER_INTRA_SCALE_TABLE" } ,\
   1168 	{0x0144, 0x00000000, 0x0000FFFF, 0, "CR_SKIPPED_CODED_SCALE_TABLE" } ,\
   1169 	{0x0148, 0x00000000, 0x007FFFFF, 0, "CR_POLYNOM_ALPHA_COEFF_CORE_0" } ,\
   1170 	{0x014C, 0x00000000, 0x0003FFFF, 0, "CR_POLYNOM_GAMMA_COEFF_CORE_0" } ,\
   1171 	{0x0150, 0x0000071C, 0x00000FFF, 0, "CR_POLYNOM_CUTOFF_CORE_0" } ,\
   1172 	{0x0154, 0x00000000, 0x007FFFFF, 0, "CR_POLYNOM_ALPHA_COEFF_CORE_1" } ,\
   1173 	{0x0158, 0x00000000, 0x0003FFFF, 0, "CR_POLYNOM_GAMMA_COEFF_CORE_1" } ,\
   1174 	{0x015C, 0x0000071C, 0x00000FFF, 0, "CR_POLYNOM_CUTOFF_CORE_1" } ,\
   1175 	{0x0160, 0x00000000, 0x007FFFFF, 0, "CR_POLYNOM_ALPHA_COEFF_CORE_2" } ,\
   1176 	{0x0164, 0x00000000, 0x0003FFFF, 0, "CR_POLYNOM_GAMMA_COEFF_CORE_2" } ,\
   1177 	{0x0168, 0x0000071C, 0x00000FFF, 0, "CR_POLYNOM_CUTOFF_CORE_2" } ,\
   1178 	{0x0300, 0x00000000, 0xFFFFFFFF, 0, "CR_FIRMWARE_REG_4" } ,\
   1179 	{0x0304, 0x00000000, 0xFFFFFFFF, 0, "CR_FIRMWARE_REG_5" } ,\
   1180 	{0x0308, 0x00000000, 0xFFFFFFFF, 0, "CR_FIRMWARE_REG_6" } ,\
   1181 	{0x030C, 0x00000000, 0xFFFFFFFF, 0, "CR_FIRMWARE_REG_7" } ,\
   1182 	{0x03B0, 0x00000000, 0x000000FF, 0, "CR_MULTICORE_RSVD0" } ,\
   1183 	{0x03C0, 0x04070000, 0xFFFFFFFF, 1, "CR_TOPAZHP_CORE_ID" } ,\
   1184 	{0x03D0, 0x00030203, 0xFFFFFFFF, 1, "CR_TOPAZHP_CORE_REV" } ,\
   1185 	{0x03E0, 0xFFFFFF00, 0xFFFFFF80, 1, "CR_TOPAZHP_CORE_DES1" } ,\
   1186 	{0x03F0, 0x00000000, 0xFFFFFFFF, 1, "CR_TOPAZHP_CORE_DES2" } ,\
   1187 { 0 }}
   1188 
   1189 #define TOPAZHP_TOP_REGS_INIT(uBase) \
   1190 	{ \
   1191 		int n;\
   1192 		TOPAZHP_TOP_REG_DEFAULT_TABLE;\
   1193 		for (n = 0; n < sizeof(TOPAZHP_TOP_Defaults)/ sizeof(TOPAZHP_TOP_Defaults[0] ) -1; n++)\
   1194 		{\
   1195 			RegWriteNoTrap(TOPAZHP_TOP_Defaults[n].uRegOffset + uBase, TOPAZHP_TOP_Defaults[n].uRegDefault); \
   1196 		}\
   1197 	}
   1198 #endif
   1199