/external/llvm/lib/Target/Lanai/ |
LanaiAluCode.h | 38 SRA = 0x37, 97 case SRA: 115 .Case("sha", SRA) 139 case ISD::SRA: 140 return AluCode::SRA;
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
ARMSelectionDAGInfo.h | 28 case ISD::SRA: return ARM_AM::asr;
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/external/llvm/lib/Target/ARM/ |
ARMSelectionDAGInfo.h | 29 case ISD::SRA: return ARM_AM::asr;
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/external/llvm/lib/Target/X86/ |
X86TargetTransformInfo.cpp | 102 // normally expanded to the sequence SRA + SRL + ADD + SRA. 119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. 137 { ISD::SRA, MVT::v16i32, 1 }, 140 { ISD::SRA, MVT::v8i64, 1 }, 153 { ISD::SRA, MVT::v4i32, 1 }, 156 { ISD::SRA, MVT::v8i32, 1 }, 180 { ISD::SRA, MVT::v16i8, 2 }, 183 { ISD::SRA, MVT::v8i16, 2 }, 186 { ISD::SRA, MVT::v4i32, 2 } [all...] |
/prebuilts/go/darwin-x86/src/cmd/internal/obj/arm/ |
anames.go | 65 "SRA",
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/prebuilts/go/darwin-x86/src/cmd/internal/obj/mips/ |
anames.go | 83 "SRA",
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/prebuilts/go/linux-x86/src/cmd/internal/obj/arm/ |
anames.go | 65 "SRA",
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/prebuilts/go/linux-x86/src/cmd/internal/obj/mips/ |
anames.go | 83 "SRA",
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/external/pcre/dist2/src/sljit/ |
sljitNativeSPARC_32.c | 60 return push_inst(compiler, SRA | D(dst) | S1(dst) | IMM(24), DR(dst)); 71 return push_inst(compiler, (op == SLJIT_MOV_S16 ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst)); 112 FAIL_IF(push_inst(compiler, SRA | D(TMP_REG1) | S1(dst) | IMM(31), DR(TMP_REG1))); 134 FAIL_IF(push_inst(compiler, SRA | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst)));
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sljitNativeMIPS_32.c | 91 return push_inst(compiler, SRA | T(dst) | D(dst) | SH_IMM(24), DR(dst)); 109 return push_inst(compiler, SRA | T(dst) | D(dst) | SH_IMM(16), DR(dst)); 312 FAIL_IF(push_inst(compiler, SRA | T(dst) | DA(UGREATER_FLAG) | SH_IMM(31), UGREATER_FLAG)); 336 EMIT_SHIFT(SRA, SRAV);
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/system/core/libpixelflinger/codeflinger/ |
MIPSAssembler.cpp | 394 case ASR: mMips->SRA(tmpReg, amode.reg, amode.value); break; 505 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break; 537 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break; [all...] |
MIPS64Assembler.cpp | 381 case ASR: mMips->SRA(tmpReg, amode.reg, amode.value); break; 504 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break; 531 case ASR: mMips->SRA(Rd, amode.reg, amode.value); break; 1078 mMips->SRA(R_at, Rm, 16); 1086 mMips->SRA(R_at2, Rs, 16); [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts. 65 SHL, SRA, SRL
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
ISDOpcodes.h | 317 SHL, SRA, SRL, ROTL, ROTR, 375 // SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
MSP430ISelLowering.h | 64 /// SHL, SRA, SRL - Non-constant shifts. 65 SHL, SRA, SRL
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/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeIntegerTypes.cpp | 86 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; 678 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS); [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
LegalizeIntegerTypes.cpp | 73 case ISD::SRA: Res = PromoteIntRes_SRA(N); break; 552 return DAG.getNode(ISD::SRA, N->getDebugLoc(), [all...] |
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/MmcHostDxe/ |
MmcHostDxe.c | 435 MmioWrite32 (MMCHS_SYSCTL, SRA);
437 while ((MmioRead32 (MMCHS_SYSCTL) & SRA) != 0x0);
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/device/linaro/bootloader/edk2/Omap35xxPkg/MmcHostDxe/ |
MmcHostDxe.c | 435 MmioWrite32 (MMCHS_SYSCTL, SRA);
437 while ((MmioRead32 (MMCHS_SYSCTL) & SRA) != 0x0);
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/external/valgrind/none/tests/mips64/ |
shift_instructions.c | 10 SRA, SRAV, SRL, SRLV 177 case SRA: 178 TEST2("sra $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1); 179 TEST2("sra $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3); 180 TEST2("sra $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1); 181 TEST2("sra $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
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/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/ |
Omap3530MMCHS.h | 106 #define SRA BIT24
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/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/ |
Omap3530MMCHS.h | 106 #define SRA BIT24
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/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 339 SHL, SRA, SRL, ROTL, ROTR, 408 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to [all...] |
/external/llvm/lib/Target/AMDGPU/ |
AMDGPUTargetTransformInfo.cpp | 135 case ISD::SRA: {
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/prebuilts/clang/host/darwin-x86/clang-3957855/prebuilt_include/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 357 SHL, SRA, SRL, ROTL, ROTR, 426 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to [all...] |