| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_util.c | 280 read_mask = TGSI_WRITEMASK_XYZW;
284 read_mask = src_idx == 0 ? TGSI_WRITEMASK_XYZ : TGSI_WRITEMASK_XYZW;
320 read_mask = TGSI_WRITEMASK_XYZW;
332 read_mask = TGSI_WRITEMASK_XYZW;
338 read_mask = TGSI_WRITEMASK_XYZW;
|
| tgsi_lowering.c | 411 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) {
416 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_XYZW);
428 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_XYZW);
459 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) {
464 reg_dst(&new_inst.Dst[0], &ctx->tmp[A].dst, TGSI_WRITEMASK_XYZW);
473 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_XYZW);
505 if (dst->Register.WriteMask & TGSI_WRITEMASK_XYZW) {
529 reg_dst(&new_inst.Dst[0], dst, TGSI_WRITEMASK_XYZW);
[all...] |
| tgsi_point_sprite.c | 256 ts->point_size_tmp, TGSI_WRITEMASK_XYZW);
285 TGSI_WRITEMASK_XYZW,
347 TGSI_WRITEMASK_XYZW,
357 TGSI_WRITEMASK_XYZW);
383 dstReg, TGSI_WRITEMASK_XYZW);
|
| tgsi_emulate.c | 90 new_inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW;
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| tgsi_ureg.c | 288 assert(usage_mask <= TGSI_WRITEMASK_XYZW);
338 ureg->nr_input_regs, TGSI_WRITEMASK_XYZW, array_id, array_size);
479 return ureg_DECL_output_masked(ureg, name, index, TGSI_WRITEMASK_XYZW,
491 TGSI_WRITEMASK_XYZW,
[all...] |
| tgsi_build.c | 106 declaration.UsageMask = TGSI_WRITEMASK_XYZW;
1012 dst_register.WriteMask = TGSI_WRITEMASK_XYZW;
1034 assert( mask <= TGSI_WRITEMASK_XYZW );
[all...] |
| tgsi_transform.h | 195 decl.Declaration.UsageMask = TGSI_WRITEMASK_XYZW;
|
| tgsi_ureg.h | [all...] |
| tgsi_dump.c | 223 if (writemask != TGSI_WRITEMASK_XYZW) {
|
| tgsi_scan.c | 880 dst->Register.WriteMask != TGSI_WRITEMASK_XYZW)
|
| /external/mesa3d/src/mesa/state_tracker/ |
| st_atifs_to_tgsi.c | 722 inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW;
738 inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW;
749 inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW;
764 inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW;
775 inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW;
786 inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW;
798 inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW;
811 inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW;
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| st_cb_drawpixels_shader.c | 152 TGSI_WRITEMASK_XYZW,
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| st_tgsi_lower_yuv.c | 240 ctx->tmp[i].dst.Register.WriteMask = TGSI_WRITEMASK_XYZW;
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| st_mesa_to_tgsi.c | 351 (negate_mask == 0 || negate_mask == TGSI_WRITEMASK_XYZW))
[all...] |
| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_tgsi_info.c | 142 readmask = TGSI_WRITEMASK_XYZW;
149 readmask = TGSI_WRITEMASK_XYZW;
235 readmask = TGSI_WRITEMASK_XYZW;
|
| lp_bld_tgsi_aos.c | 312 if (reg->Register.WriteMask != TGSI_WRITEMASK_XYZW) {
|
| /external/mesa3d/src/gallium/drivers/r300/ |
| r300_vs_draw.c | 253 new_inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW;
265 new_inst.Dst[0].Register.WriteMask = TGSI_WRITEMASK_XYZW;
|
| /external/mesa3d/src/gallium/auxiliary/util/ |
| u_pstipple.c | 345 TGSI_WRITEMASK_XYZW,
|
| u_blit.c | 68 void *fs[PIPE_MAX_TEXTURE_TYPES][TGSI_WRITEMASK_XYZW + 1][3];
596 set_fragment_shader(ctx, TGSI_WRITEMASK_XYZW,
|
| u_simple_shaders.c | 257 if (writemask != TGSI_WRITEMASK_XYZW) {
307 TGSI_WRITEMASK_XYZW,
|
| /external/mesa3d/src/gallium/include/pipe/ |
| p_shader_tokens.h | 97 #define TGSI_WRITEMASK_XYZW 0x0F
|
| /external/mesa3d/src/gallium/state_trackers/nine/ |
| nine_ff.c | 668 tmp.WriteMask = TGSI_WRITEMASK_XYZW;
694 tmp.WriteMask = TGSI_WRITEMASK_XYZW;
707 writemask = TGSI_WRITEMASK_XYZW;
[all...] |
| /external/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| fd2_compiler.c | 529 tmp_dst->WriteMask = TGSI_WRITEMASK_XYZW;
|
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_fpc_optimize.c | 587 current->FullInstruction.Dst[0].Register.WriteMask == TGSI_WRITEMASK_XYZW &&
|
| /external/mesa3d/src/gallium/drivers/llvmpipe/ |
| lp_bld_interp.c | 736 bld->mask[0] = TGSI_WRITEMASK_XYZW;
|
