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    Searched refs:TSFlags (Results 1 - 25 of 71) sorted by null

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  /external/llvm/lib/Target/AMDGPU/
SIInstrInfo.h 184 return MI.getDesc().TSFlags & SIInstrFlags::SALU;
188 return get(Opcode).TSFlags & SIInstrFlags::SALU;
192 return MI.getDesc().TSFlags & SIInstrFlags::VALU;
196 return get(Opcode).TSFlags & SIInstrFlags::VALU;
208 return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
212 return get(Opcode).TSFlags & SIInstrFlags::SOP1;
216 return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
220 return get(Opcode).TSFlags & SIInstrFlags::SOP2;
224 return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
228 return get(Opcode).TSFlags & SIInstrFlags::SOPC
    [all...]
R600Defines.h 62 #define IS_VTX(desc) ((desc).TSFlags & R600_InstFlag::VTX_INST)
63 #define IS_TEX(desc) ((desc).TSFlags & R600_InstFlag::TEX_INST)
SIInsertWaits.cpp 185 uint64_t TSFlags = MI.getDesc().TSFlags;
188 Result.Named.VM = !!(TSFlags & SIInstrFlags::VM_CNT);
191 Result.Named.EXP = !!(TSFlags & SIInstrFlags::EXP_CNT &&
195 if (TSFlags & SIInstrFlags::LGKM_CNT) {
R600InstrInfo.cpp 35 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG;
39 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR;
126 unsigned TargetFlags = get(Opcode).TSFlags;
132 unsigned TargetFlags = get(Opcode).TSFlags;
140 unsigned TargetFlags = get(Opcode).TSFlags;
192 return (get(Opcode).TSFlags & R600_InstFlag::IS_EXPORT);
    [all...]
R600OptimizeVectorRegisters.cpp 135 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
251 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
336 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) {
  /external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
X86MCCodeEmitter.cpp 115 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
121 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
125 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte,
129 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
150 /// in an instruction with the specified TSFlags.
151 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
152 unsigned Size = X86II::getSizeOfImm(TSFlags);
153 bool isPCRel = X86II::isImmPCRel(TSFlags);
243 uint64_t TSFlags, unsigned &CurByte,
271 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0
    [all...]
X86BaseInfo.h 417 static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
418 return TSFlags >> X86II::OpcodeShift;
421 static inline bool hasImm(uint64_t TSFlags) {
422 return (TSFlags & X86II::ImmMask) != 0;
425 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
427 static inline unsigned getSizeOfImm(uint64_t TSFlags) {
428 switch (TSFlags & X86II::ImmMask) {
441 /// TSFlags indicates that it is pc relative.
442 static inline unsigned isImmPCRel(uint64_t TSFlags) {
443 switch (TSFlags & X86II::ImmMask)
    [all...]
  /external/llvm/lib/Target/X86/MCTargetDesc/
X86MCCodeEmitter.cpp 126 uint64_t TSFlags, bool Rex, unsigned &CurByte,
134 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
141 bool emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
145 uint8_t DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
165 static bool isCDisp8(uint64_t TSFlags, int Value, int& CValue) {
166 assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) &&
170 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift;
189 /// in an instruction with the specified TSFlags.
190 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
191 unsigned Size = X86II::getSizeOfImm(TSFlags);
    [all...]
X86BaseInfo.h 564 inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) {
565 return TSFlags >> X86II::OpcodeShift;
568 inline bool hasImm(uint64_t TSFlags) {
569 return (TSFlags & X86II::ImmMask) != 0;
572 /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field
574 inline unsigned getSizeOfImm(uint64_t TSFlags) {
575 switch (TSFlags & X86II::ImmMask) {
589 /// TSFlags indicates that it is pc relative.
590 inline unsigned isImmPCRel(uint64_t TSFlags) {
591 switch (TSFlags & X86II::ImmMask)
    [all...]
  /external/llvm/lib/Target/NVPTX/
NVPTXReplaceImageHandles.cpp 83 if (MCID.TSFlags & NVPTXII::IsTexFlag) {
89 if (!(MCID.TSFlags & NVPTXII::IsTexModeUnifiedFlag)) {
95 } else if (MCID.TSFlags & NVPTXII::IsSuldMask) {
97 1 << (((MCID.TSFlags & NVPTXII::IsSuldMask) >> NVPTXII::IsSuldShift) - 1);
105 } else if (MCID.TSFlags & NVPTXII::IsSustFlag) {
112 } else if (MCID.TSFlags & NVPTXII::IsSurfTexQueryFlag) {
NVPTXInstrInfo.cpp 70 // Look for the appropriate part of TSFlags
73 unsigned TSFlags =
74 (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift;
75 isMove = (TSFlags == 1);
94 unsigned TSFlags =
95 (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift;
96 isLoad = (TSFlags == 1);
105 unsigned TSFlags =
106 (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift;
107 isStore = (TSFlags == 1)
    [all...]
  /external/llvm/lib/Target/ARM/
ARMHazardRecognizer.cpp 23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
54 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
  /external/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCInstrInfo.cpp 170 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
178 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
185 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
251 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
269 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
275 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
283 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
298 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
316 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
322 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
    [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/ARM/
ARMHazardRecognizer.cpp 23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask;
47 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) {
54 (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) {
ARMCodeEmitter.cpp 452 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
532 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
    [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/X86/
X86CodeEmitter.cpp 154 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
156 if (Desc.TSFlags & X86II::REX_W)
175 switch (Desc.TSFlags & X86II::FormMask) {
631 if (Desc->TSFlags & X86II::LOCK)
635 switch (Desc->TSFlags & X86II::SegOvrMask) {
647 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP)
651 if (Desc->TSFlags & X86II::OpSize)
655 if (Desc->TSFlags & X86II::AdSize)
659 switch (Desc->TSFlags & X86II::Op0Mask) {
683 (((Desc->TSFlags & X86II::Op0Mask)-X86II::D8
    [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
PPCHazardRecognizers.cpp 81 uint64_t TSFlags = MCID.TSFlags;
83 isFirst = TSFlags & PPCII::PPC970_First;
84 isSingle = TSFlags & PPCII::PPC970_Single;
85 isCracked = TSFlags & PPCII::PPC970_Cracked;
86 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
  /external/llvm/lib/Target/WebAssembly/InstPrinter/
WebAssemblyInstPrinter.cpp 100 : (Desc.TSFlags & WebAssemblyII::VariableOpImmediateIsLabel)))
142 MII.get(MI->getOpcode()).TSFlags == 0) &&
143 "WebAssembly variable_ops register ops don't use TSFlags");
158 (MII.get(MI->getOpcode()).TSFlags &
162 // TODO: (MII.get(MI->getOpcode()).TSFlags &
171 assert(Desc.TSFlags == 0 &&
172 "WebAssembly variable_ops floating point ops don't use TSFlags");
184 (MII.get(MI->getOpcode()).TSFlags &
  /external/llvm/lib/Target/AMDGPU/MCTargetDesc/
R600MCCodeEmitter.cpp 133 ((Desc.TSFlags & R600_InstFlag::OP1) ||
134 Desc.TSFlags & R600_InstFlag::OP2)) {
160 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
  /external/llvm/lib/Target/PowerPC/
PPCHazardRecognizers.cpp 290 uint64_t TSFlags = MCID.TSFlags;
292 isFirst = TSFlags & PPCII::PPC970_First;
293 isSingle = TSFlags & PPCII::PPC970_Single;
294 isCracked = TSFlags & PPCII::PPC970_Cracked;
295 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
  /external/swiftshader/third_party/LLVM/lib/Target/Mips/
MipsCodeEmitter.cpp 147 uint64_t TSFlags = MI.getDesc().TSFlags;
148 uint64_t Form = TSFlags & MipsII::FormMask;
239 if ((MI.getDesc().TSFlags & MipsII::FormMask) == MipsII::Pseudo)
  /external/llvm/lib/Target/X86/InstPrinter/
X86ATTInstPrinter.cpp 43 uint64_t TSFlags = Desc.TSFlags;
50 if (TSFlags & X86II::LOCK)
X86IntelInstPrinter.cpp 39 uint64_t TSFlags = Desc.TSFlags;
41 if (TSFlags & X86II::LOCK)
  /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/
MBlazeMCCodeEmitter.cpp 184 uint64_t TSFlags = Desc.TSFlags;
191 switch ((TSFlags & MBlazeII::FormMask)) {
  /external/llvm/lib/Target/Hexagon/
HexagonInstrInfo.cpp     [all...]

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