1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __TSPD_PRIVATE_H__ 32 #define __TSPD_PRIVATE_H__ 33 34 #include <arch.h> 35 #include <context.h> 36 #include <interrupt_mgmt.h> 37 #include <platform_def.h> 38 #include <psci.h> 39 40 /******************************************************************************* 41 * Secure Payload PM state information e.g. SP is suspended, uninitialised etc 42 * and macros to access the state information in the per-cpu 'state' flags 43 ******************************************************************************/ 44 #define TSP_PSTATE_OFF 0 45 #define TSP_PSTATE_ON 1 46 #define TSP_PSTATE_SUSPEND 2 47 #define TSP_PSTATE_SHIFT 0 48 #define TSP_PSTATE_MASK 0x3 49 #define get_tsp_pstate(state) ((state >> TSP_PSTATE_SHIFT) & TSP_PSTATE_MASK) 50 #define clr_tsp_pstate(state) (state &= ~(TSP_PSTATE_MASK \ 51 << TSP_PSTATE_SHIFT)) 52 #define set_tsp_pstate(st, pst) do { \ 53 clr_tsp_pstate(st); \ 54 st |= (pst & TSP_PSTATE_MASK) << \ 55 TSP_PSTATE_SHIFT; \ 56 } while (0); 57 58 59 /* 60 * This flag is used by the TSPD to determine if the TSP is servicing a standard 61 * SMC request prior to programming the next entry into the TSP e.g. if TSP 62 * execution is preempted by a non-secure interrupt and handed control to the 63 * normal world. If another request which is distinct from what the TSP was 64 * previously doing arrives, then this flag will be help the TSPD to either 65 * reject the new request or service it while ensuring that the previous context 66 * is not corrupted. 67 */ 68 #define STD_SMC_ACTIVE_FLAG_SHIFT 2 69 #define STD_SMC_ACTIVE_FLAG_MASK 1 70 #define get_std_smc_active_flag(state) ((state >> STD_SMC_ACTIVE_FLAG_SHIFT) \ 71 & STD_SMC_ACTIVE_FLAG_MASK) 72 #define set_std_smc_active_flag(state) (state |= \ 73 1 << STD_SMC_ACTIVE_FLAG_SHIFT) 74 #define clr_std_smc_active_flag(state) (state &= \ 75 ~(STD_SMC_ACTIVE_FLAG_MASK \ 76 << STD_SMC_ACTIVE_FLAG_SHIFT)) 77 78 /******************************************************************************* 79 * Secure Payload execution state information i.e. aarch32 or aarch64 80 ******************************************************************************/ 81 #define TSP_AARCH32 MODE_RW_32 82 #define TSP_AARCH64 MODE_RW_64 83 84 /******************************************************************************* 85 * The SPD should know the type of Secure Payload. 86 ******************************************************************************/ 87 #define TSP_TYPE_UP PSCI_TOS_NOT_UP_MIG_CAP 88 #define TSP_TYPE_UPM PSCI_TOS_UP_MIG_CAP 89 #define TSP_TYPE_MP PSCI_TOS_NOT_PRESENT_MP 90 91 /******************************************************************************* 92 * Secure Payload migrate type information as known to the SPD. We assume that 93 * the SPD is dealing with an MP Secure Payload. 94 ******************************************************************************/ 95 #define TSP_MIGRATE_INFO TSP_TYPE_MP 96 97 /******************************************************************************* 98 * Number of cpus that the present on this platform. TODO: Rely on a topology 99 * tree to determine this in the future to avoid assumptions about mpidr 100 * allocation 101 ******************************************************************************/ 102 #define TSPD_CORE_COUNT PLATFORM_CORE_COUNT 103 104 /******************************************************************************* 105 * Constants that allow assembler code to preserve callee-saved registers of the 106 * C runtime context while performing a security state switch. 107 ******************************************************************************/ 108 #define TSPD_C_RT_CTX_X19 0x0 109 #define TSPD_C_RT_CTX_X20 0x8 110 #define TSPD_C_RT_CTX_X21 0x10 111 #define TSPD_C_RT_CTX_X22 0x18 112 #define TSPD_C_RT_CTX_X23 0x20 113 #define TSPD_C_RT_CTX_X24 0x28 114 #define TSPD_C_RT_CTX_X25 0x30 115 #define TSPD_C_RT_CTX_X26 0x38 116 #define TSPD_C_RT_CTX_X27 0x40 117 #define TSPD_C_RT_CTX_X28 0x48 118 #define TSPD_C_RT_CTX_X29 0x50 119 #define TSPD_C_RT_CTX_X30 0x58 120 #define TSPD_C_RT_CTX_SIZE 0x60 121 #define TSPD_C_RT_CTX_ENTRIES (TSPD_C_RT_CTX_SIZE >> DWORD_SHIFT) 122 123 /******************************************************************************* 124 * Constants that allow assembler code to preserve caller-saved registers of the 125 * SP context while performing a TSP preemption. 126 * Note: These offsets have to match with the offsets for the corresponding 127 * registers in cpu_context as we are using memcpy to copy the values from 128 * cpu_context to sp_ctx. 129 ******************************************************************************/ 130 #define TSPD_SP_CTX_X0 0x0 131 #define TSPD_SP_CTX_X1 0x8 132 #define TSPD_SP_CTX_X2 0x10 133 #define TSPD_SP_CTX_X3 0x18 134 #define TSPD_SP_CTX_X4 0x20 135 #define TSPD_SP_CTX_X5 0x28 136 #define TSPD_SP_CTX_X6 0x30 137 #define TSPD_SP_CTX_X7 0x38 138 #define TSPD_SP_CTX_X8 0x40 139 #define TSPD_SP_CTX_X9 0x48 140 #define TSPD_SP_CTX_X10 0x50 141 #define TSPD_SP_CTX_X11 0x58 142 #define TSPD_SP_CTX_X12 0x60 143 #define TSPD_SP_CTX_X13 0x68 144 #define TSPD_SP_CTX_X14 0x70 145 #define TSPD_SP_CTX_X15 0x78 146 #define TSPD_SP_CTX_X16 0x80 147 #define TSPD_SP_CTX_X17 0x88 148 #define TSPD_SP_CTX_SIZE 0x90 149 #define TSPD_SP_CTX_ENTRIES (TSPD_SP_CTX_SIZE >> DWORD_SHIFT) 150 151 #ifndef __ASSEMBLY__ 152 153 #include <cassert.h> 154 #include <stdint.h> 155 156 /* 157 * The number of arguments to save during a SMC call for TSP. 158 * Currently only x1 and x2 are used by TSP. 159 */ 160 #define TSP_NUM_ARGS 0x2 161 162 /* AArch64 callee saved general purpose register context structure. */ 163 DEFINE_REG_STRUCT(c_rt_regs, TSPD_C_RT_CTX_ENTRIES); 164 165 /* 166 * Compile time assertion to ensure that both the compiler and linker 167 * have the same double word aligned view of the size of the C runtime 168 * register context. 169 */ 170 CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \ 171 assert_spd_c_rt_regs_size_mismatch); 172 173 /* SEL1 Secure payload (SP) caller saved register context structure. */ 174 DEFINE_REG_STRUCT(sp_ctx_regs, TSPD_SP_CTX_ENTRIES); 175 176 /* 177 * Compile time assertion to ensure that both the compiler and linker 178 * have the same double word aligned view of the size of the C runtime 179 * register context. 180 */ 181 CASSERT(TSPD_SP_CTX_SIZE == sizeof(sp_ctx_regs_t), \ 182 assert_spd_sp_regs_size_mismatch); 183 184 /******************************************************************************* 185 * Structure which helps the SPD to maintain the per-cpu state of the SP. 186 * 'saved_spsr_el3' - temporary copy to allow FIQ handling when the TSP has been 187 * preempted. 188 * 'saved_elr_el3' - temporary copy to allow FIQ handling when the TSP has been 189 * preempted. 190 * 'state' - collection of flags to track SP state e.g. on/off 191 * 'mpidr' - mpidr to associate a context with a cpu 192 * 'c_rt_ctx' - stack address to restore C runtime context from after 193 * returning from a synchronous entry into the SP. 194 * 'cpu_ctx' - space to maintain SP architectural state 195 * 'saved_tsp_args' - space to store arguments for TSP arithmetic operations 196 * which will queried using the TSP_GET_ARGS SMC by TSP. 197 * 'sp_ctx' - space to save the SEL1 Secure Payload(SP) caller saved 198 * register context after it has been preempted by an EL3 199 * routed NS interrupt and when a Secure Interrupt is taken 200 * to SP. 201 ******************************************************************************/ 202 typedef struct tsp_context { 203 uint64_t saved_elr_el3; 204 uint32_t saved_spsr_el3; 205 uint32_t state; 206 uint64_t mpidr; 207 uint64_t c_rt_ctx; 208 cpu_context_t cpu_ctx; 209 uint64_t saved_tsp_args[TSP_NUM_ARGS]; 210 #if TSPD_ROUTE_IRQ_TO_EL3 211 sp_ctx_regs_t sp_ctx; 212 #endif 213 } tsp_context_t; 214 215 /* Helper macros to store and retrieve tsp args from tsp_context */ 216 #define store_tsp_args(tsp_ctx, x1, x2) do {\ 217 tsp_ctx->saved_tsp_args[0] = x1;\ 218 tsp_ctx->saved_tsp_args[1] = x2;\ 219 } while (0) 220 221 #define get_tsp_args(tsp_ctx, x1, x2) do {\ 222 x1 = tsp_ctx->saved_tsp_args[0];\ 223 x2 = tsp_ctx->saved_tsp_args[1];\ 224 } while (0) 225 226 /* TSPD power management handlers */ 227 extern const spd_pm_ops_t tspd_pm; 228 229 /******************************************************************************* 230 * Forward declarations 231 ******************************************************************************/ 232 struct tsp_vectors; 233 234 /******************************************************************************* 235 * Function & Data prototypes 236 ******************************************************************************/ 237 uint64_t tspd_enter_sp(uint64_t *c_rt_ctx); 238 void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret); 239 uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx); 240 void __dead2 tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret); 241 void tspd_init_tsp_ep_state(struct entry_point_info *tsp_ep, 242 uint32_t rw, 243 uint64_t pc, 244 tsp_context_t *tsp_ctx); 245 246 extern tsp_context_t tspd_sp_context[TSPD_CORE_COUNT]; 247 extern struct tsp_vectors *tsp_vectors; 248 #endif /*__ASSEMBLY__*/ 249 250 #endif /* __TSPD_PRIVATE_H__ */ 251
