/external/llvm/lib/Target/X86/ |
X86FixupSetCC.cpp | 163 unsigned ZeroReg = MRI->createVirtualRegister(RC); 168 ZeroReg); 174 .addReg(ZeroReg)
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X86FrameLowering.cpp | 509 // ZeroReg = 0 512 // FinalReg = !Flags.Ovf ? TestReg : ZeroReg 552 ZeroReg = InProlog ? (unsigned)X86::RCX 598 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg) 599 .addReg(ZeroReg, RegState::Undef) 600 .addReg(ZeroReg, RegState::Undef); 607 .addReg(ZeroReg); [all...] |
/external/swiftshader/third_party/subzero/src/ |
IceTargetLoweringX8664.cpp | 350 Variable *ZeroReg = RebasePtr; 369 assert(ZeroReg == Base || AbsoluteAddress || isAssignedToRspOrRbp(Base)); 371 // If Mem is an absolute address, no need to update ZeroReg (which is 373 ZeroReg = Base; 385 ZeroReg = Base; 400 // If the Index is not shifted, and it is a Valid Base, and the ZeroReg is 401 // still RebasePtr, then we do ZeroReg = Index, and hopefully prevent the 404 if (Shift == 0 && isAssignedToRspOrRbp(Index) && ZeroReg == RebasePtr) { 405 ZeroReg = Index; 432 if (Base != nullptr && Base != ZeroReg) [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
MipsInstrInfo.cpp | 106 unsigned Opc = 0, ZeroReg = 0; 110 Opc = Mips::ADDu, ZeroReg = Mips::ZERO; 138 Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64; 158 if (ZeroReg) 159 MIB.addReg(ZeroReg);
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/external/llvm/lib/Target/Mips/ |
MipsSEISelDAGToDAG.cpp | 89 unsigned DstReg = 0, ZeroReg = 0; 96 ZeroReg = Mips::ZERO; 101 ZeroReg = Mips::ZERO_64; 107 // Replace uses with ZeroReg. 121 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg)) 124 MO.setReg(ZeroReg); [all...] |
MipsSEInstrInfo.cpp | 83 unsigned Opc = 0, ZeroReg = 0; 91 Opc = Mips::OR, ZeroReg = Mips::ZERO; 147 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; 178 if (ZeroReg) 179 MIB.addReg(ZeroReg); 475 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 494 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
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MipsAsmPrinter.cpp | 122 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; 123 TmpInst0.addOperand(MCOperand::createReg(ZeroReg)); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64InstrInfo.cpp | [all...] |
AArch64ExpandPseudoInsts.cpp | 57 unsigned ExtendImm, unsigned ZeroReg, 599 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, 634 BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg) [all...] |
AArch64FastISel.cpp | 345 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; 348 ResultReg).addReg(ZeroReg, getKillRegState(true)); [all...] |
/external/llvm/lib/Target/Mips/AsmParser/ |
MipsAsmParser.cpp | [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCInstrInfo.cpp | [all...] |
PPCISelLowering.cpp | [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
PPCISelLowering.cpp | [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
ARMFastISel.cpp | [all...] |
/external/llvm/lib/Target/ARM/ |
ARMFastISel.cpp | [all...] |