1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __FVP_PWRC_H__ 32 #define __FVP_PWRC_H__ 33 34 /* FVP Power controller register offset etc */ 35 #define PPOFFR_OFF 0x0 36 #define PPONR_OFF 0x4 37 #define PCOFFR_OFF 0x8 38 #define PWKUPR_OFF 0xc 39 #define PSYSR_OFF 0x10 40 41 #define PWKUPR_WEN (1ull << 31) 42 43 #define PSYSR_AFF_L2 (1 << 31) 44 #define PSYSR_AFF_L1 (1 << 30) 45 #define PSYSR_AFF_L0 (1 << 29) 46 #define PSYSR_WEN (1 << 28) 47 #define PSYSR_PC (1 << 27) 48 #define PSYSR_PP (1 << 26) 49 50 #define PSYSR_WK_SHIFT 24 51 #define PSYSR_WK_MASK 0x3 52 #define PSYSR_WK(x) (x >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK 53 54 #define WKUP_COLD 0x0 55 #define WKUP_RESET 0x1 56 #define WKUP_PPONR 0x2 57 #define WKUP_GICREQ 0x3 58 59 #define PSYSR_INVALID 0xffffffff 60 61 #ifndef __ASSEMBLY__ 62 63 /******************************************************************************* 64 * Function & variable prototypes 65 ******************************************************************************/ 66 int fvp_pwrc_setup(void); 67 void fvp_pwrc_write_pcoffr(unsigned long); 68 void fvp_pwrc_write_ppoffr(unsigned long); 69 void fvp_pwrc_write_pponr(unsigned long); 70 void fvp_pwrc_set_wen(unsigned long); 71 void fvp_pwrc_clr_wen(unsigned long); 72 unsigned int fvp_pwrc_read_psysr(unsigned long); 73 unsigned int fvp_pwrc_get_cpu_wkr(unsigned long); 74 75 #endif /*__ASSEMBLY__*/ 76 77 #endif /* __FVP_PWRC_H__ */ 78
