1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch.h> 32 #include <arch_helpers.h> 33 #include <arm_gic.h> 34 #include <assert.h> 35 #include <bl_common.h> 36 #include <bl31.h> 37 #include <console.h> 38 #include <mmio.h> 39 #include <platform.h> 40 #include <stddef.h> 41 #include "drivers/pwrc/fvp_pwrc.h" 42 #include "fvp_def.h" 43 #include "fvp_private.h" 44 45 /******************************************************************************* 46 * Declarations of linker defined symbols which will help us find the layout 47 * of trusted SRAM 48 ******************************************************************************/ 49 extern unsigned long __RO_START__; 50 extern unsigned long __RO_END__; 51 extern unsigned long __BL31_END__; 52 53 #if USE_COHERENT_MEM 54 extern unsigned long __COHERENT_RAM_START__; 55 extern unsigned long __COHERENT_RAM_END__; 56 #endif 57 58 /* 59 * The next 3 constants identify the extents of the code, RO data region and the 60 * limit of the BL3-1 image. These addresses are used by the MMU setup code and 61 * therefore they must be page-aligned. It is the responsibility of the linker 62 * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols 63 * refer to page-aligned addresses. 64 */ 65 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 66 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 67 #define BL31_END (unsigned long)(&__BL31_END__) 68 69 #if USE_COHERENT_MEM 70 /* 71 * The next 2 constants identify the extents of the coherent memory region. 72 * These addresses are used by the MMU setup code and therefore they must be 73 * page-aligned. It is the responsibility of the linker script to ensure that 74 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols 75 * refer to page-aligned addresses. 76 */ 77 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 78 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 79 #endif 80 81 #if RESET_TO_BL31 82 static entry_point_info_t bl32_image_ep_info; 83 static entry_point_info_t bl33_image_ep_info; 84 #else 85 /******************************************************************************* 86 * Reference to structure which holds the arguments that have been passed to 87 * BL31 from BL2. 88 ******************************************************************************/ 89 static bl31_params_t *bl2_to_bl31_params; 90 #endif 91 92 /******************************************************************************* 93 * Return a pointer to the 'entry_point_info' structure of the next image for the 94 * security state specified. BL33 corresponds to the non-secure image type 95 * while BL32 corresponds to the secure image type. A NULL pointer is returned 96 * if the image does not exist. 97 ******************************************************************************/ 98 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 99 { 100 #if RESET_TO_BL31 101 assert(sec_state_is_valid(type)); 102 103 if (type == NON_SECURE) 104 return &bl33_image_ep_info; 105 else 106 return &bl32_image_ep_info; 107 #else 108 entry_point_info_t *next_image_info; 109 110 assert(sec_state_is_valid(type)); 111 112 next_image_info = (type == NON_SECURE) ? 113 bl2_to_bl31_params->bl33_ep_info : 114 bl2_to_bl31_params->bl32_ep_info; 115 116 /* None of the images on this platform can have 0x0 as the entrypoint */ 117 if (next_image_info->pc) 118 return next_image_info; 119 else 120 return NULL; 121 #endif 122 } 123 124 /******************************************************************************* 125 * Return a pointer to the 'image_info' structure of the next image for the 126 * security state specified. BL33 corresponds to the non-secure image type 127 * while BL32 corresponds to the secure image type. A NULL pointer is returned 128 * if the image does not exist. 129 ******************************************************************************/ 130 image_info_t *bl31_plat_get_next_image_image_info(uint32_t type) 131 { 132 #if RESET_TO_BL31 133 assert(sec_state_is_valid(type)); 134 135 if (type == NON_SECURE) 136 return NULL; 137 else 138 return NULL; 139 #else 140 image_info_t *next_image_info; 141 142 assert(sec_state_is_valid(type)); 143 144 next_image_info = (type == NON_SECURE) ? 145 bl2_to_bl31_params->bl33_image_info : 146 bl2_to_bl31_params->bl32_image_info; 147 148 /* None of the images on this platform can have size 0x0 */ 149 if (next_image_info->image_size) 150 return next_image_info; 151 else 152 return NULL; 153 #endif 154 } 155 156 157 158 /******************************************************************************* 159 * Perform any BL31 specific platform actions. Here is an opportunity to copy 160 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 161 * are lost (potentially). This needs to be done before the MMU is initialized 162 * so that the memory layout can be used while creating page tables. On the FVP 163 * we know that BL2 has populated the parameters in secure DRAM. So we just use 164 * the reference passed in 'from_bl2' instead of copying. The 'data' parameter 165 * is not used since all the information is contained in 'from_bl2'. Also, BL2 166 * has flushed this information to memory, so we are guaranteed to pick up good 167 * data 168 ******************************************************************************/ 169 void bl31_early_platform_setup(bl31_params_t *from_bl2, 170 void *plat_params_from_bl2) 171 { 172 /* Initialize the console to provide early debug support */ 173 console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); 174 175 /* Initialize the platform config for future decision making */ 176 fvp_config_setup(); 177 178 #if RESET_TO_BL31 179 /* There are no parameters from BL2 if BL31 is a reset vector */ 180 assert(from_bl2 == NULL); 181 assert(plat_params_from_bl2 == NULL); 182 183 /* 184 * Do initial security configuration to allow DRAM/device access. On 185 * Base FVP only DRAM security is programmable (via TrustZone), but 186 * other platforms might have more programmable security devices 187 * present. 188 */ 189 fvp_security_setup(); 190 191 /* Populate entry point information for BL3-2 and BL3-3 */ 192 SET_PARAM_HEAD(&bl32_image_ep_info, 193 PARAM_EP, 194 VERSION_1, 195 0); 196 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 197 bl32_image_ep_info.pc = BL32_BASE; 198 bl32_image_ep_info.spsr = fvp_get_spsr_for_bl32_entry(); 199 200 SET_PARAM_HEAD(&bl33_image_ep_info, 201 PARAM_EP, 202 VERSION_1, 203 0); 204 /* 205 * Tell BL31 where the non-trusted software image 206 * is located and the entry state information 207 */ 208 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 209 bl33_image_ep_info.spsr = fvp_get_spsr_for_bl33_entry(); 210 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 211 212 #else 213 /* Check params passed from BL2 should not be NULL, 214 * We are not checking plat_params_from_bl2 as NULL as we are not 215 * using it on FVP 216 */ 217 assert(from_bl2 != NULL); 218 assert(from_bl2->h.type == PARAM_BL31); 219 assert(from_bl2->h.version >= VERSION_1); 220 221 bl2_to_bl31_params = from_bl2; 222 assert(((unsigned long)plat_params_from_bl2) == FVP_BL31_PLAT_PARAM_VAL); 223 #endif 224 } 225 226 /******************************************************************************* 227 * Initialize the gic, configure the CLCD and zero out variables needed by the 228 * secondaries to boot up correctly. 229 ******************************************************************************/ 230 void bl31_platform_setup(void) 231 { 232 unsigned int reg_val; 233 234 /* Initialize the gic cpu and distributor interfaces */ 235 fvp_gic_init(); 236 arm_gic_setup(); 237 238 /* 239 * TODO: Configure the CLCD before handing control to 240 * linux. Need to see if a separate driver is needed 241 * instead. 242 */ 243 mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGDATA, 0); 244 mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL, 245 (1ull << 31) | (1 << 30) | (7 << 20) | (0 << 16)); 246 247 /* Enable and initialize the System level generic timer */ 248 mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); 249 250 /* Allow access to the System counter timer module */ 251 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); 252 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); 253 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); 254 mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val); 255 mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val); 256 257 reg_val = (1 << CNTNSAR_NS_SHIFT(0)) | (1 << CNTNSAR_NS_SHIFT(1)); 258 mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val); 259 260 /* Intialize the power controller */ 261 fvp_pwrc_setup(); 262 263 /* Topologies are best known to the platform. */ 264 fvp_setup_topology(); 265 } 266 267 /******************************************************************************* 268 * Perform the very early platform specific architectural setup here. At the 269 * moment this is only intializes the mmu in a quick and dirty way. 270 ******************************************************************************/ 271 void bl31_plat_arch_setup(void) 272 { 273 fvp_cci_init(); 274 #if RESET_TO_BL31 275 fvp_cci_enable(); 276 #endif 277 fvp_configure_mmu_el3(BL31_RO_BASE, 278 (BL31_END - BL31_RO_BASE), 279 BL31_RO_BASE, 280 BL31_RO_LIMIT 281 #if USE_COHERENT_MEM 282 , BL31_COHERENT_RAM_BASE, 283 BL31_COHERENT_RAM_LIMIT 284 #endif 285 ); 286 } 287
