| /external/mesa3d/src/intel/vulkan/ |
| anv_nir_lower_push_constants.c | 44 assert(intrin->const_index[0] % 4 == 0);
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| anv_nir_apply_dynamic_offsets.c | 59 unsigned set = res_intrin->const_index[0];
60 unsigned binding = res_intrin->const_index[1];
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| anv_nir_apply_pipeline_layout.c | 133 unsigned *const_index, unsigned array_size,
170 *const_index += MIN2(deref_array->base_offset, array_size - 1);
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vec4_gs_nir.cpp | 71 instr->const_index[0] + offset_reg->u32[0],
89 instr->const_index[0] + offset_reg->u32[0],
94 if (instr->const_index[0] == VARYING_SLOT_PSIZ)
110 int stream_id = instr->const_index[0];
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| brw_nir.c | 52 * This pass adds constant offsets to instr->const_index[0], and resets
74 intrin->const_index[0] += const_offset->u32[0];
113 int attr = intrin->const_index[0];
116 intrin->const_index[0] = 4 * slot;
133 int vue_slot = vue_map->varying_to_slot[intrin->const_index[0]];
135 intrin->const_index[0] = vue_slot;
219 int vue_slot = vue_map->varying_to_slot[intrin->const_index[0]];
221 intrin->const_index[0] = vue_slot;
227 intrin->const_index[0] += const_vertex->u32[0] *
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| brw_vec4_tcs.cpp | 272 unsigned imm_offset = instr->const_index[0];
318 unsigned imm_offset = instr->const_index[0];
330 unsigned mask = instr->const_index[1];
334 unsigned imm_offset = instr->const_index[0];
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| brw_nir_attribute_workarounds.c | 54 uint8_t wa_flags = state->wa_flags[intrin->const_index[0]];
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| brw_fs_nir.cpp | [all...] |
| brw_vec4_tes.cpp | 199 unsigned imm_offset = instr->const_index[0];
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| brw_vec4_nir.cpp | 347 * into instr->const_index[0].
423 src = src_reg(ATTR, instr->const_index[0] + const_offset->u32[0],
445 int varying = instr->const_index[0] + const_offset->u32[0];
541 unsigned write_mask = instr->const_index[0];
830 indirect, brw_imm_ud(instr->const_index[1]));
839 (unsigned) instr->const_index[0];
[all...] |
| /external/mesa3d/src/compiler/glsl/ |
| ast_array_index.cpp | 170 ir_constant *const const_index = idx->constant_expression_value(); local
171 if (const_index != NULL && idx->type->is_integer()) {
172 const int idx = const_index->value.i[0];
215 } else if (const_index == NULL && array->type->is_array()) {
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| lower_buffer_access.cpp | 406 ir_constant *const_index = local
408 if (const_index) {
409 *const_offset += array_stride * const_index->value.u[0];
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| opt_algebraic.cpp | 66 int const_index,
252 ir_algebraic_visitor::reassociate_constant(ir_expression *ir1, int const_index,
274 reassociate_operands(ir1, const_index, ir2, 1);
277 reassociate_operands(ir1, const_index, ir2, 0);
281 if (reassociate_constant(ir1, const_index, constant,
287 if (reassociate_constant(ir1, const_index, constant,
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| lower_ubo_reference.cpp | 203 ir_constant *const_index = a->array_index->as_constant(); local
205 if (!const_index) {
227 const_index->get_uint_component(0),
[all...] |
| glsl_to_nir.cpp | 2102 ir_constant *const_index = ir->array_index->as_constant(); local
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_optimize.c | 721 int const_index = -1; local
766 if (const_index != -1) {
770 const_index = i;
774 if (!rc_src_reg_is_immediate(c, inst_mul->U.I.SrcReg[const_index].File,
775 inst_mul->U.I.SrcReg[const_index].Index)) {
779 inst_mul->U.I.SrcReg[const_index].Index,
780 inst_mul->U.I.SrcReg[const_index].Swizzle,
781 inst_mul->U.I.SrcReg[const_index].Negate,
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| /external/mesa3d/src/compiler/nir/ |
| nir_instr_set.c | 136 hash = _mesa_fnv32_1a_accumulate_block(hash, instr->const_index,
138 * sizeof(instr->const_index[0]));
385 if (intrinsic1->const_index[i] != intrinsic2->const_index[i])
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| nir_builder.h | 462 store->const_index[0] = writemask & ((1 << num_components) - 1);
497 load->const_index[0] = index;
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| nir_clone.c | 362 memcpy(nitr->const_index, itr->const_index, sizeof(nitr->const_index));
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| nir.h | 936 int const_index[NIR_INTRINSIC_MAX_CONST_INDEX]; member in struct:__anon27427
968 * Indicates the usage of a const_index slot.
1053 /** indicates the usage of intr->const_index[n] */
1069 return instr->const_index[info->index_map[NIR_INTRINSIC_##flag] - 1]; \
1076 instr->const_index[info->index_map[NIR_INTRINSIC_##flag] - 1] = val; \
[all...] |
| nir_print.c | 576 fprintf(fp, "%d", instr->const_index[i]);
606 fprintf(fp, " %s=%d", index_name[idx], instr->const_index[off]);
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| /external/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| instr-a2xx.h | 352 uint8_t const_index : 5; member in struct:PACKED
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| disasm-a2xx.c | 350 printf(" CONST(%u, %u)", vtx->const_index, vtx->const_index_sel);
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| ir-a2xx.c | 306 vtx->const_index = instr->fetch.const_idx;
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| /external/mesa3d/src/amd/common/ |
| ac_nir_to_llvm.c | 2022 unsigned const_index; local
2118 unsigned const_index; local
[all...] |
