| /art/compiler/optimizing/ |
| code_generator.cc | 1335 const uint32_t core_spills = codegen->GetSlowPathSpills(locations, \/* core_registers *\/ true); local
1359 const uint32_t core_spills = codegen->GetSlowPathSpills(locations, \/* core_registers *\/ true); local
[all...] |
| register_allocation_resolver.cc | 279 size_t core_spills = local
284 core_register_spill_size * core_spills + fp_register_spill_size * fp_spills;
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| code_generator_arm64.cc | 174 const uint32_t core_spills = codegen->GetSlowPathSpills(locations, /* core_registers */ true); local
176 DCHECK(ArtVixlRegCodeCoherentForRegSet(core_spills,
181 CPURegList core_list = CPURegList(CPURegister::kRegister, kXRegSize, core_spills);
218 const uint32_t core_spills = codegen->GetSlowPathSpills(locations, /* core_registers */ true); local
219 for (uint32_t i : LowToHighBits(core_spills)) {
[all...] |
| code_generator_arm_vixl.cc | 283 const uint32_t core_spills = codegen->GetSlowPathSpills(locations, /* core_registers */ true); local
284 for (uint32_t i : LowToHighBits(core_spills)) {
296 arm_codegen->GetAssembler()->StoreRegisterList(core_spills, orig_offset);
321 const uint32_t core_spills = codegen->GetSlowPathSpills(locations, /* core_registers */ true); local
322 for (uint32_t i : LowToHighBits(core_spills)) {
330 arm_codegen->GetAssembler()->LoadRegisterList(core_spills, orig_offset);
[all...] |
| /art/oatdump/ |
| oatdump.cc | [all...] |
