| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| etnaviv_translate.h | 368 * with the samplers if the GPU does hot support the HALIGN feature.
375 unsigned *paddingX, unsigned *paddingY, unsigned *halign)
381 *halign = rs_align ? TEXTURE_HALIGN_SIXTEEN : TEXTURE_HALIGN_FOUR;
386 *halign = rs_align ? TEXTURE_HALIGN_SIXTEEN : TEXTURE_HALIGN_FOUR;
391 *halign = TEXTURE_HALIGN_SUPER_TILED;
396 *halign = TEXTURE_HALIGN_SPLIT_TILED;
401 *halign = TEXTURE_HALIGN_SPLIT_SUPER_TILED;
|
| etnaviv_resource.h | 68 unsigned halign; member in struct:etna_resource
|
| etnaviv_resource.c | 177 unsigned halign = TEXTURE_HALIGN_FOUR; local
179 &paddingY, &halign);
197 rsc->halign = halign;
|
| etnaviv_texture.c | 136 /* If we have HALIGN support, we can allow for the RS padding */
141 /* Non-HALIGN GPUs only accept 4x4 tile-aligned textures */
142 if (res->halign != TEXTURE_HALIGN_FOUR)
212 VIVS_TE_SAMPLER_CONFIG1_HALIGN(res->halign);
|
| etnaviv_transfer.c | 158 /* HALIGN 4 resources are incompatible with the resolve engine,
160 rsc->halign != TEXTURE_HALIGN_FOUR)) {
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_tex_layout.c | 271 const unsigned int halign = 64; local
281 img_width = ALIGN(width, halign);
317 mip1_width = ALIGN_NPOT(minify(mt->physical_width0, 1), mt->halign) +
320 mip1_width = ALIGN_NPOT(minify(mt->physical_width0, 1), mt->halign) +
354 x += ALIGN_NPOT(width, mt->halign) / bw;
374 return ALIGN_NPOT(minify(mt->physical_width0, level), mt->halign);
526 unsigned wL = ALIGN_NPOT(WL, mt->halign);
736 mt->halign = 64;
743 mt->halign = 128 / mt->cpp;
750 _mesa_get_format_block_size(mt->format, &mt->halign, &mt->valign)
[all...] |
| intel_mipmap_tree.h | 436 uint32_t halign; member in struct:intel_mipmap_tree
[all...] |
| intel_mipmap_tree.c | 740 assert(brw->gen < 8 || mt->halign == 16 || num_samples <= 1);
[all...] |
| /external/mesa3d/src/gallium/drivers/swr/ |
| swr_screen.cpp | 607 const unsigned width = align(res->swr.width, res->swr.halign);
685 * Each level's sizes are subject to the valign and halign settings of the
704 res->swr.halign = KNOB_MACROTILE_X_DIM;
707 res->swr.halign = 1;
711 unsigned halign = res->swr.halign * util_format_get_blockwidth(fmt); local
712 unsigned width = align(pt->width0, halign);
715 width += align(u_minify(pt->width0, level), halign);
723 // widths. This can happen if, e.g. halign is 32, and the width of level
730 align(u_minify(pt->width0, 1), halign)
[all...] |
| /external/libnl/doc/stylesheets/ |
| volnitsky.css | 415 th.tableblock.halign-left, td.tableblock.halign-left {
418 th.tableblock.halign-center, td.tableblock.halign-center {
421 th.tableblock.halign-right, td.tableblock.halign-right {
|
| asciidoc.css | 508 th.tableblock.halign-left, td.tableblock.halign-left {
511 th.tableblock.halign-center, td.tableblock.halign-center {
514 th.tableblock.halign-right, td.tableblock.halign-right {
|
| flask.css | 500 th.tableblock.halign-left, td.tableblock.halign-left {
503 th.tableblock.halign-center, td.tableblock.halign-center {
506 th.tableblock.halign-right, td.tableblock.halign-right {
|
| /external/webrtc/webrtc/examples/peerconnection/client/linux/ |
| main_wnd.cc | 259 GtkWidget* halign = gtk_alignment_new(1, 0, 0, 0); local
260 gtk_container_add(GTK_CONTAINER(halign), hbox);
261 gtk_box_pack_start(GTK_BOX(vbox_), halign, FALSE, FALSE, 0); local
|
| /hardware/qcom/display/sdm845/libdrmutils/ |
| drm_interface.h | 358 int halign; member in struct:sde_drm::DRMConnectorInfo
|
| /external/mesa3d/src/gallium/drivers/swr/rasterizer/memory/ |
| TilingFunctions.h | 260 /// @param hAlign - horizontal alignment per miip, in texels
266 uint32_t hAlign,
277 // @note hAlign is already in blocks for compressed formats so upconvert
281 hAlign *= info.bcWidth;
284 offset = GFX_ALIGN(curWidth, hAlign);
288 offset += GFX_ALIGN(curWidth, hAlign);
301 /// @param hAlign - horizontal alignment per mip, in texels
307 uint32_t hAlign,
318 // @note hAlign is already in blocks for compressed formats so upconvert
322 hAlign *= info.bcWidth
[all...] |
| /external/mesa3d/src/gallium/drivers/swr/rasterizer/core/ |
| state.h | 504 uint32_t halign; member in struct:SWR_SURFACE_STATE
[all...] |
| /external/bison/doc/ |
| refcard.tex | 260 \def\paralign{\vskip\parskip\halign}
|
| /hardware/qcom/display/sdm845/sdm/libs/core/drm/ |
| hw_device_drm.cpp | 443 hw_panel_info_.height_align = connector_info_.halign;
[all...] |
| /external/e2fsprogs/doc/ |
| texinfo.tex | [all...] |
| /external/e2fsprogs/lib/et/ |
| texinfo.tex | [all...] |
| /external/bison/build-aux/ |
| texinfo.tex | [all...] |
| /external/libmicrohttpd/doc/ |
| texinfo.tex | [all...] |
| /external/python/cpython2/Modules/_ctypes/libffi/ |
| texinfo.tex | [all...] |
| /toolchain/binutils/binutils-2.25/texinfo/ |
| texinfo.tex | [all...] |
| /external/netperf/doc/ |
| texinfo.tex | [all...] |
