| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| ld-zero-3.s | 3 lwu $0, 0x12345678($2)
|
| r6-64.s | 40 lwu $4, (-262144 << 2)($pc)
41 lwu $4, (262143 << 2)($pc)
|
| ld-zero-3.d | 10 [0-9a-f]+ <[^>]*> lwu zero,22136\(at\)
|
| mipsr6@ld-zero-3.d | 11 [0-9a-f]+ <[^>]*> lwu zero,22136\(at\)
|
| micromips@ld-zero-3.d | 12 [0-9a-f]+ <[^>]*> lwu zero,1656\(at\)
|
| mips16-64.d | 74 d4: bb40 lwu v0,0\(v1\)
75 d6: f000 bb41 lwu v0,1\(v1\)
76 da: f000 bb42 lwu v0,2\(v1\)
77 de: f000 bb43 lwu v0,3\(v1\)
78 e2: bb41 lwu v0,4\(v1\)
79 e4: bb42 lwu v0,8\(v1\)
80 e6: bb44 lwu v0,16\(v1\)
81 e8: bb48 lwu v0,32\(v1\)
82 ea: bb50 lwu v0,64\(v1\)
83 ec: f080 bb40 lwu v0,128\(v1\
[all...] |
| mips16.d | 73 d4: bb40 lwu v0,0\(v1\)
74 d6: f000 bb41 lwu v0,1\(v1\)
75 da: f000 bb42 lwu v0,2\(v1\)
76 de: f000 bb43 lwu v0,3\(v1\)
77 e2: bb41 lwu v0,4\(v1\)
78 e4: bb42 lwu v0,8\(v1\)
79 e6: bb44 lwu v0,16\(v1\)
80 e8: bb48 lwu v0,32\(v1\)
81 ea: bb50 lwu v0,64\(v1\)
82 ec: f080 bb40 lwu v0,128\(v1\
[all...] |
| mips16.s | 45 ldst lwu, $2, $3
|
| micromips.s | [all...] |
| /external/llvm/test/MC/Mips/micromips64r6/ |
| invalid-wrong-error.s | 10 # The LWU instruction with invalid memory operand should emit "expected memory with 12-bit signed offset".
11 lwu $31, 4096($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
12 lwu $31, 2048($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
13 lwu $31, -2049($31) # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
|
| /art/runtime/interpreter/mterp/mips64/ |
| footer.S | 59 lwu a1, OFF_FP_DEX_PC(rFP)
|
| header.S | 192 lwu \reg, 0(AT)
|
| /external/llvm/test/MC/Mips/ |
| micromips-loadstore-instructions.s | 25 # CHECK-EL: lwu $2, 8($4) # encoding: [0x44,0x60,0x08,0xe0]
71 # CHECK-EB: lwu $2, 8($4) # encoding: [0x60,0x44,0xe0,0x08]
114 lwu $2, 8($4)
|
| micromips-invalid.s | 91 lwu $32, 4096($32) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /art/runtime/arch/mips64/ |
| quick_entrypoints_mips64.S | 970 lwu $t3, 0($t1)
973 lwu $t3, 4($t1)
982 lwu $t3, 0($t1)
991 lwu $t3, 0($t1)
993 lwu $t9, 4($t1)
[all...] |
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips3.s | 59 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset
|
| invalid-mips4.s | 74 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips3.s | 55 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:24: error: expected memory with 12-bit signed offset
|
| invalid-mips4.s | 51 lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset
|
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 139 lwu $s3,-24086($v1)
269 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 144 lwu $s3,-24086($v1)
298 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 145 lwu $s3,-24086($v1)
300 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 152 lwu $s3,-24086($v1)
319 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 168 lwu $s3,-24086($v1)
347 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 168 lwu $s3,-24086($v1)
346 lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
|
