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      1 /*
      2  * Copyright (C) 2016 The Android Open Source Project
      3  *
      4  * Licensed under the Apache License, Version 2.0 (the "License");
      5  * you may not use this file except in compliance with the License.
      6  * You may obtain a copy of the License at
      7  *
      8  *      http://www.apache.org/licenses/LICENSE-2.0
      9  *
     10  * Unless required by applicable law or agreed to in writing, software
     11  * distributed under the License is distributed on an "AS IS" BASIS,
     12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     13  * See the License for the specific language governing permissions and
     14  * limitations under the License.
     15  */
     16 
     17 #include <machine/regdef.h>
     18 
     19 /* TODO: add the missing file and use its FP register definitions. */
     20 /* #include <machine/fpregdef.h> */
     21 /* FP register definitions */
     22 #define f0  $$f0
     23 #define f1  $$f1
     24 #define f2  $$f2
     25 #define f3  $$f3
     26 #define f12 $$f12
     27 #define f13 $$f13
     28 
     29 /*
     30  * It looks like the GNU assembler currently does not support the blec and bgtc
     31  * idioms, which should translate into bgec and bltc respectively with swapped
     32  * left and right register operands.
     33  * TODO: remove these macros when the assembler is fixed.
     34  */
     35 .macro blec lreg, rreg, target
     36     bgec    \rreg, \lreg, \target
     37 .endm
     38 .macro bgtc lreg, rreg, target
     39     bltc    \rreg, \lreg, \target
     40 .endm
     41 
     42 /*
     43 Mterp and MIPS64 notes:
     44 
     45 The following registers have fixed assignments:
     46 
     47   reg nick      purpose
     48   s0  rPC       interpreted program counter, used for fetching instructions
     49   s1  rFP       interpreted frame pointer, used for accessing locals and args
     50   s2  rSELF     self (Thread) pointer
     51   s3  rINST     first 16-bit code unit of current instruction
     52   s4  rIBASE    interpreted instruction base pointer, used for computed goto
     53   s5  rREFS     base of object references in shadow frame  (ideally, we'll get rid of this later).
     54   s6  rPROFILE  jit profile hotness countdown
     55 */
     56 
     57 /* During bringup, we'll use the shadow frame model instead of rFP */
     58 /* single-purpose registers, given names for clarity */
     59 #define rPC      s0
     60 #define rFP      s1
     61 #define rSELF    s2
     62 #define rINST    s3
     63 #define rIBASE   s4
     64 #define rREFS    s5
     65 #define rPROFILE s6
     66 
     67 /*
     68  * This is a #include, not a %include, because we want the C pre-processor
     69  * to expand the macros into assembler assignment statements.
     70  */
     71 #include "asm_support.h"
     72 
     73 /*
     74  * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs.  So,
     75  * to access other shadow frame fields, we need to use a backwards offset.  Define those here.
     76  */
     77 #define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET)
     78 #define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET)
     79 #define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET)
     80 #define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET)
     81 #define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET)
     82 #define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET)
     83 #define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET)
     84 #define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET)
     85 #define OFF_FP_SHADOWFRAME OFF_FP(0)
     86 
     87 #define MTERP_PROFILE_BRANCHES 1
     88 #define MTERP_LOGGING 0
     89 
     90 /*
     91  * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects.  Must
     92  * be done *before* something throws.
     93  *
     94  * It's okay to do this more than once.
     95  *
     96  * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped
     97  * dex byte codes.  However, the rest of the runtime expects dex pc to be an instruction
     98  * offset into the code_items_[] array.  For effiency, we will "export" the
     99  * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC
    100  * to convert to a dex pc when needed.
    101  */
    102 .macro EXPORT_PC
    103     sd      rPC, OFF_FP_DEX_PC_PTR(rFP)
    104 .endm
    105 
    106 /*
    107  * Refresh handler table.
    108  */
    109 .macro REFRESH_IBASE
    110     ld      rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF)
    111 .endm
    112 
    113 /*
    114  * Fetch the next instruction from rPC into rINST.  Does not advance rPC.
    115  */
    116 .macro FETCH_INST
    117     lhu     rINST, 0(rPC)
    118 .endm
    119 
    120 /* Advance rPC by some number of code units. */
    121 .macro ADVANCE count
    122     daddu   rPC, rPC, (\count) * 2
    123 .endm
    124 
    125 /*
    126  * Fetch the next instruction from an offset specified by _reg and advance xPC.
    127  * xPC to point to the next instruction.  "_reg" must specify the distance
    128  * in bytes, *not* 16-bit code units, and may be a signed value.  Must not set flags.
    129  *
    130  */
    131 .macro FETCH_ADVANCE_INST_RB reg
    132     daddu   rPC, rPC, \reg
    133     FETCH_INST
    134 .endm
    135 
    136 /*
    137  * Fetch the next instruction from the specified offset.  Advances rPC
    138  * to point to the next instruction.
    139  *
    140  * This must come AFTER anything that can throw an exception, or the
    141  * exception catch may miss.  (This also implies that it must come after
    142  * EXPORT_PC.)
    143  */
    144 .macro FETCH_ADVANCE_INST count
    145     ADVANCE \count
    146     FETCH_INST
    147 .endm
    148 
    149 /*
    150  * Similar to FETCH_ADVANCE_INST, but does not update rPC.  Used to load
    151  * rINST ahead of possible exception point.  Be sure to manually advance rPC
    152  * later.
    153  */
    154 .macro PREFETCH_INST count
    155     lhu     rINST, ((\count) * 2)(rPC)
    156 .endm
    157 
    158 /*
    159  * Put the instruction's opcode field into the specified register.
    160  */
    161 .macro GET_INST_OPCODE reg
    162     and     \reg, rINST, 255
    163 .endm
    164 
    165 /*
    166  * Begin executing the opcode in _reg.
    167  */
    168 .macro GOTO_OPCODE reg
    169     .set noat
    170     sll     AT, \reg, 7
    171     daddu   AT, rIBASE, AT
    172     jic     AT, 0
    173     .set at
    174 .endm
    175 
    176 /*
    177  * Get/set the 32-bit value from a Dalvik register.
    178  * Note, GET_VREG does sign extension to 64 bits while
    179  * GET_VREG_U does zero extension to 64 bits.
    180  * One is useful for arithmetic while the other is
    181  * useful for storing the result value as 64-bit.
    182  */
    183 .macro GET_VREG reg, vreg
    184     .set noat
    185     dlsa    AT, \vreg, rFP, 2
    186     lw      \reg, 0(AT)
    187     .set at
    188 .endm
    189 .macro GET_VREG_U reg, vreg
    190     .set noat
    191     dlsa    AT, \vreg, rFP, 2
    192     lwu     \reg, 0(AT)
    193     .set at
    194 .endm
    195 .macro GET_VREG_FLOAT reg, vreg
    196     .set noat
    197     dlsa    AT, \vreg, rFP, 2
    198     lwc1    \reg, 0(AT)
    199     .set at
    200 .endm
    201 .macro SET_VREG reg, vreg
    202     .set noat
    203     dlsa    AT, \vreg, rFP, 2
    204     sw      \reg, 0(AT)
    205     dlsa    AT, \vreg, rREFS, 2
    206     sw      zero, 0(AT)
    207     .set at
    208 .endm
    209 .macro SET_VREG_OBJECT reg, vreg
    210     .set noat
    211     dlsa    AT, \vreg, rFP, 2
    212     sw      \reg, 0(AT)
    213     dlsa    AT, \vreg, rREFS, 2
    214     sw      \reg, 0(AT)
    215     .set at
    216 .endm
    217 .macro SET_VREG_FLOAT reg, vreg
    218     .set noat
    219     dlsa    AT, \vreg, rFP, 2
    220     swc1    \reg, 0(AT)
    221     dlsa    AT, \vreg, rREFS, 2
    222     sw      zero, 0(AT)
    223     .set at
    224 .endm
    225 
    226 /*
    227  * Get/set the 64-bit value from a Dalvik register.
    228  * Avoid unaligned memory accesses.
    229  * Note, SET_VREG_WIDE clobbers the register containing the value being stored.
    230  * Note, SET_VREG_DOUBLE clobbers the register containing the Dalvik register number.
    231  */
    232 .macro GET_VREG_WIDE reg, vreg
    233     .set noat
    234     dlsa    AT, \vreg, rFP, 2
    235     lw      \reg, 0(AT)
    236     lw      AT, 4(AT)
    237     dinsu   \reg, AT, 32, 32
    238     .set at
    239 .endm
    240 .macro GET_VREG_DOUBLE reg, vreg
    241     .set noat
    242     dlsa    AT, \vreg, rFP, 2
    243     lwc1    \reg, 0(AT)
    244     lw      AT, 4(AT)
    245     mthc1   AT, \reg
    246     .set at
    247 .endm
    248 .macro SET_VREG_WIDE reg, vreg
    249     .set noat
    250     dlsa    AT, \vreg, rFP, 2
    251     sw      \reg, 0(AT)
    252     drotr32 \reg, \reg, 0
    253     sw      \reg, 4(AT)
    254     dlsa    AT, \vreg, rREFS, 2
    255     sw      zero, 0(AT)
    256     sw      zero, 4(AT)
    257     .set at
    258 .endm
    259 .macro SET_VREG_DOUBLE reg, vreg
    260     .set noat
    261     dlsa    AT, \vreg, rREFS, 2
    262     sw      zero, 0(AT)
    263     sw      zero, 4(AT)
    264     dlsa    AT, \vreg, rFP, 2
    265     swc1    \reg, 0(AT)
    266     mfhc1   \vreg, \reg
    267     sw      \vreg, 4(AT)
    268     .set at
    269 .endm
    270 
    271 /*
    272  * On-stack offsets for spilling/unspilling callee-saved registers
    273  * and the frame size.
    274  */
    275 #define STACK_OFFSET_RA 0
    276 #define STACK_OFFSET_GP 8
    277 #define STACK_OFFSET_S0 16
    278 #define STACK_OFFSET_S1 24
    279 #define STACK_OFFSET_S2 32
    280 #define STACK_OFFSET_S3 40
    281 #define STACK_OFFSET_S4 48
    282 #define STACK_OFFSET_S5 56
    283 #define STACK_OFFSET_S6 64
    284 #define STACK_SIZE      80    /* needs 16 byte alignment */
    285 
    286 /* Constants for float/double_to_int/long conversions */
    287 #define INT_MIN             0x80000000
    288 #define INT_MIN_AS_FLOAT    0xCF000000
    289 #define INT_MIN_AS_DOUBLE   0xC1E0000000000000
    290 #define LONG_MIN            0x8000000000000000
    291 #define LONG_MIN_AS_FLOAT   0xDF000000
    292 #define LONG_MIN_AS_DOUBLE  0xC3E0000000000000
    293