| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| mips32r2-fp32.d | 11 0+0004 <[^>]*> 44f10000 mthc1 \$17,\$f0
|
| mips32r2-fp32.s | 13 mthc1 $17, $f0
|
| li-d.d | 21 [0-9a-f]+ <[^>]*> mthc1 at,\$f0
24 [0-9a-f]+ <[^>]*> mthc1 at,\$f0
27 [0-9a-f]+ <[^>]*> mthc1 at,\$f0
|
| micromips@mips32r2-fp32.d | 12 [0-9a-f]+ <[^>]*> 5620 383b mthc1 \$17,\$f0
|
| mips32r2-ill-fp64.s | 56 mthc1 $17, $f0
57 mthc1 $17, $f1
|
| mips32r2-ill.s | 56 mthc1 $17, $f0
57 mthc1 $17, $f1 # warn
|
| mipsr6@mips32r2-ill.s | 55 mthc1 $17, $f0
|
| micromips.s | [all...] |
| mxu.s | 113 mthc1 $2, $2
114 mthc1 $2, $f2
|
| micromips-insn32.d | [all...] |
| micromips-noinsn32.d | [all...] |
| micromips-trap.d | [all...] |
| micromips.d | [all...] |
| /art/runtime/arch/mips/ |
| asm_support_mips.S | 68 /* mips32r5 & mips32r6 have mthc1 op, and have 64-bit fp regs,
76 mthc1 \temp, \feven
91 mthc1 \rodd, \feven
95 /* mips32r1 has no mthc1 op;
|
| /external/llvm/test/MC/Mips/mips32/ |
| invalid-mips32r2.s | 22 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips4/ |
| invalid-mips64r2.s | 27 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips64r2.s | 31 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64/ |
| invalid-mips64r2.s | 24 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /art/runtime/interpreter/mterp/mips64/ |
| header.S | 245 mthc1 AT, \reg
|
| /external/llvm/test/MC/Mips/ |
| micromips-fpu-instructions.s | 57 # CHECK-EL: mthc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x38]
122 # CHECK-EB: mthc1 $6, $f8 # encoding: [0x54,0xc8,0x38,0x3b]
183 mthc1 $6, $f8
|
| mips-fpu-instructions.s | 173 # CHECK: mthc1 $17, $f6 # encoding: [0x00,0x30,0xf1,0x44]
208 mthc1 $17, $f6
|
| /art/runtime/interpreter/mterp/mips/ |
| header.S | 178 mthc1 r, flo
650 mthc1 AT, rlo; \
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32r2.s | 53 mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| valid.s | 199 mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b]
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| valid.s | 302 mthc1 $11, $f12 # CHECK: mthc1 $11, $f12 # encoding: [0x55,0x6c,0x38,0x3b]
[all...] |
