| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| mips32-dspr2.s | 30 mul_s.ph $16,$17,$18
|
| mips32-dspr2.d | 31 0+0054 <[^>]*> 7e328398 mul_s\.ph s0,s1,s2
|
| mipsr6@mips32-dspr2.d | 32 0+0054 <[^>]*> 7e328398 mul_s\.ph s0,s1,s2
|
| micromips@mips32-dspr2.d | 32 0+0052 <[^>]*> 0251 842d mul_s\.ph s0,s1,s2
|
| /external/valgrind/none/tests/mips32/ |
| mips32_dspr2.stdout.exp | [all...] |
| /external/llvm/test/MC/Mips/micromips-dspr2/ |
| valid.s | 115 mul_s.ph $1, $2, $3 # CHECK: mul_s.ph $1, $2, $3 # encoding: [0x00,0x62,0x0c,0x2d]
|
| /external/llvm/test/MC/Mips/dspr2/ |
| valid.s | 94 mul_s.ph $18, $19, $20 # CHECK: mul_s.ph $18, $19, $20 # encoding: [0x7e,0x74,0x93,0x98]
|
| /external/swiftshader/third_party/subzero/src/ |
| IceAssemblerMIPS32.h | 243 void mul_s(const Operand *OpFd, const Operand *OpFs, const Operand *OpFt);
|
| IceAssemblerMIPS32.cpp | 934 void AssemblerMIPS32::mul_s(const Operand *OpFd, const Operand *OpFs, function in class:Ice::MIPS32::AssemblerMIPS32
[all...] |
| IceInstMIPS32.cpp | [all...] |
| /external/llvm/test/MC/Mips/mips32r2/ |
| invalid-dspr2.s | 76 mul_s.ph $10,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/v8/src/mips/ |
| assembler-mips.h | 883 void mul_s(FPURegister fd, FPURegister fs, FPURegister ft);
[all...] |
| macro-assembler-mips.cc | [all...] |
| assembler-mips.cc | 2496 void Assembler::mul_s(FPURegister fd, FPURegister fs, FPURegister ft) { function in class:v8::Assembler
[all...] |
| /external/v8/src/mips64/ |
| assembler-mips64.h | [all...] |
| assembler-mips64.cc | 2824 void Assembler::mul_s(FPURegister fd, FPURegister fs, FPURegister ft) { function in class:v8::internal::Assembler
[all...] |
| macro-assembler-mips64.cc | [all...] |
| /external/v8/src/compiler/mips/ |
| code-generator-mips.cc | [all...] |
| /external/v8/src/compiler/mips64/ |
| code-generator-mips64.cc | [all...] |
