| /toolchain/binutils/binutils-2.25/opcodes/ |
| Makefile.am | 62 aarch64-asm.h aarch64-dis.h aarch64-opc.h aarch64-tbl.h \
63 epiphany-desc.h epiphany-opc.h \
64 fr30-desc.h fr30-opc.h \
65 frv-desc.h frv-opc.h \
66 h8500-opc.h \
68 i386-opc.h \
71 ia64-opc.h \
72 ip2k-desc.h ip2k-opc.h \
73 iq2000-desc.h iq2000-opc.h \
75 lm32-opc.h
[all...] |
| cgen.sh | 22 # Generate CGEN opcode files: arch-desc.[ch], arch-opc.[ch],
27 # arch-file opc-file options [extrafiles]
36 # OPC-FILE is the name of the .opc file (including path).
90 rm -f ${tmp}-opc.h ${tmp}-opc.h1
91 rm -f ${tmp}-opc.c ${tmp}-opc.c1
99 ${cgen} ${cgendir}/cgen-opc.scm \
105 -OPC ${opcfile}
[all...] |
| nds32-dis.c | 227 nds32_parse_opcode (struct nds32_opcode *opc, bfd_vma pc ATTRIBUTE_UNUSED,
242 if (opc == NULL)
251 pstr_src = opc->instruction;
254 func (stream, "%s", opc->opcode);
260 func (stream, "%s ", opc->opcode);
268 func (stream, "%s.", opc->opcode);
269 else if (strstr (opc->instruction, "tito"))
270 func (stream, "%s", opc->opcode);
272 func (stream, "%s ", opc->opcode);
315 if ((opc->value == 0xfc00) || (opc->value == 0xfc80)
589 struct nds32_opcode *opc; local
602 struct nds32_opcode *opc; local
982 struct nds32_opcode *opc; local
[all...] |
| xtensa-dis.c | 77 xtensa_opcode opc,
93 (void) xtensa_operand_decode (isa, opc, opnd, &operand_val);
96 if (xtensa_operand_is_register (isa, opc, opnd) == 0)
98 if (xtensa_operand_is_PCrelative (isa, opc, opnd) == 1)
100 (void) xtensa_operand_undo_reloc (isa, opc, opnd,
116 xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd);
120 while (i < xtensa_operand_num_regs (isa, opc, opnd))
141 xtensa_opcode opc; local
234 opc = xtensa_opcode_decode (isa, fmt, n, slot_buffer);
236 xtensa_opcode_name (isa, opc));
[all...] |
| tic6x-dis.c | 308 const tic6x_opcode *const opc = &tic6x_opcode_table[opcode_id]; local
310 = &tic6x_insn_format_table[opc->format];
335 if (opc->flags & TIC6X_FLAG_MACRO)
380 if (opc->flags & TIC6X_FLAG_INSN16_SPRED)
439 for (fix = 0; fix < opc->num_fixed_fields; fix++)
443 = tic6x_field_from_fmt (fmt, opc->fixed_fields[fix].field_id);
448 opcode, opc->fixed_fields[fix].field_id, fix);
453 if (field_bits < opc->fixed_fields[fix].min_val
454 || field_bits > opc->fixed_fields[fix].max_val)
522 if (opc->func_unit == tic6x_func_unit_nfu
[all...] |
| makefile.vms | 26 OBJS=ia64-dis.obj,ia64-opc.obj
30 OBJS=alpha-dis.obj,alpha-opc.obj
|
| dlx-dis.c | 36 #define OPC(x) ((x >> 26) & 0x3F)
39 unsigned char opc, rs1, rs2, rd; variable
106 unsigned char r_opc[] = { OPC(ALUOP) }; /* Fix ME */
152 if (r_opc[idx] != opc)
193 { OPC(LHIOP), "lhi" }, /* Load HI to register. */
194 { OPC(LBOP), "lb" }, /* load byte sign extended. */
195 { OPC(LBUOP), "lbu" }, /* load byte unsigned. */
196 { OPC(LSBUOP),"ldstbu"}, /* load store byte unsigned. */
197 { OPC(LHOP), "lh" }, /* load halfword sign extended. */
198 { OPC(LHUOP), "lhu" }, /* load halfword unsigned. *
[all...] |
| /external/wpa_supplicant_8/src/crypto/ |
| milenage.c | 27 * @opc: OPc = 128-bit value derived from OP and K
36 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand,
44 tmp1[i] = _rand[i] ^ opc[i];
57 tmp3[(i + 8) % 16] = tmp2[i] ^ opc[i];
67 tmp1[i] ^= opc[i];
78 * @opc: OPc = 128-bit value derived from OP and K
88 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand,
96 tmp1[i] = _rand[i] ^ opc[i]
[all...] |
| milenage.h | 12 void milenage_generate(const u8 *opc, const u8 *amf, const u8 *k,
15 int milenage_auts(const u8 *opc, const u8 *k, const u8 *_rand, const u8 *auts,
17 int gsm_milenage(const u8 *opc, const u8 *k, const u8 *_rand, u8 *sres,
19 int milenage_check(const u8 *opc, const u8 *k, const u8 *sqn, const u8 *_rand,
22 int milenage_f1(const u8 *opc, const u8 *k, const u8 *_rand,
24 int milenage_f2345(const u8 *opc, const u8 *k, const u8 *_rand,
|
| /toolchain/binutils/binutils-2.25/include/ |
| xtensa-isa.h | 377 xtensa_insnbuf slotbuf, xtensa_opcode opc);
383 xtensa_opcode_name (xtensa_isa isa, xtensa_opcode opc);
403 xtensa_opcode_is_branch (xtensa_isa isa, xtensa_opcode opc);
406 xtensa_opcode_is_jump (xtensa_isa isa, xtensa_opcode opc);
409 xtensa_opcode_is_loop (xtensa_isa isa, xtensa_opcode opc);
412 xtensa_opcode_is_call (xtensa_isa isa, xtensa_opcode opc);
420 xtensa_opcode_num_operands (xtensa_isa isa, xtensa_opcode opc);
423 xtensa_opcode_num_stateOperands (xtensa_isa isa, xtensa_opcode opc);
426 xtensa_opcode_num_interfaceOperands (xtensa_isa isa, xtensa_opcode opc);
442 xtensa_opcode_num_funcUnit_uses (xtensa_isa isa, xtensa_opcode opc);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUInstrInfo.cpp | 33 unsigned opc = I->getOpcode(); local
35 return (opc == SPU::BR
36 || opc == SPU::BRA
37 || opc == SPU::BI);
42 unsigned opc = I->getOpcode(); local
44 return (opc == SPU::BRNZr32
45 || opc == SPU::BRNZv4i32
46 || opc == SPU::BRZr32
47 || opc == SPU::BRZv4i32
48 || opc == SPU::BRHNZr1
145 unsigned opc; local
180 unsigned opc; local
[all...] |
| /toolchain/binutils/binutils-2.25/bfd/ |
| xtensa-isa.c | 652 #define CHECK_OPCODE(INTISA,OPC,ERRVAL) \
654 if ((OPC) < 0 || (OPC) >= (INTISA)->num_opcodes) \
701 xtensa_opcode opc;
708 opc = (intisa->slots[slot_id].opcode_decode_fn) (slotbuf);
709 if (opc != XTENSA_UNDEFINED)
710 return opc;
720 xtensa_insnbuf slotbuf, xtensa_opcode opc)
728 CHECK_OPCODE (intisa, opc, -1);
731 encode_fn = intisa->opcodes[opc].encode_fns[slot_id]
697 xtensa_opcode opc; local
[all...] |
| /external/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| disasm-a2xx.c | 129 #define INSTR(opc, num_srcs) [opc] = { num_srcs, #opc }
439 #define INSTR(opc, name, fxn) [opc] = { name, fxn }
464 printf("%s", fetch_instructions[fetch->opc].name);
465 fetch_instructions[fetch->opc].fxn(fetch);
477 return (cf->opc == EXEC) ||
478 (cf->opc == EXEC_END) ||
479 (cf->opc == COND_EXEC) |
[all...] |
| instr-a2xx.h | 212 instr_cf_opc_t opc : 4; member in struct:PACKED
221 instr_cf_opc_t opc : 4; member in struct:PACKED
234 instr_cf_opc_t opc : 4; member in struct:PACKED
243 instr_cf_opc_t opc : 4; member in struct:PACKED
253 instr_cf_opc_t opc : 4; member in struct:PACKED::PACKED
312 instr_fetch_opc_t opc : 5; member in struct:PACKED
346 instr_fetch_opc_t opc : 5; member in struct:PACKED
381 instr_fetch_opc_t opc : 5; member in struct:PACKED::PACKED
|
| ir-a2xx.h | 73 instr_fetch_opc_t opc; member in struct:ir2_instruction::__anon27640::__anon27641
162 instr->fetch.opc = VTX_FETCH;
174 instr->fetch.opc = TEX_FETCH;
|
| /external/mesa3d/src/gallium/drivers/etnaviv/ |
| etnaviv_disasm.c | 38 uint32_t opc : 6; member in struct:instr
459 #define OPC(opc) [INST_OPCODE_##opc] = {#opc, print_opc_default}
460 #define OPC_MOV(opc) [INST_OPCODE_##opc] = {#opc, print_opc_mov}
461 #define OPC_TEX(opc) [INST_OPCODE_##opc] = {#opc, print_opc_tex
522 const unsigned opc = instr->opc | (instr->opcode_bit6 << 6); local
[all...] |
| /external/mesa3d/src/gallium/drivers/freedreno/ir3/ |
| ir3_cp.c | 68 if (src_instr->opc == OPC_META_FO)
75 if (src_instr->opc == OPC_META_PHI)
115 switch (opc_cat(instr->opc)) {
145 valid_flags = ir3_cat2_absneg(instr->opc) |
148 if (ir3_cat2_int(instr->opc))
173 valid_flags = ir3_cat3_absneg(instr->opc) |
320 if (instr->opc == OPC_META_PHI)
366 if ((n == 1) && is_mad(instr->opc) &&
400 if ((opc_cat(instr->opc) == 3) && (n == 2) &&
436 debug_assert((opc_cat(instr->opc) == 1) |
[all...] |
| instr-a3xx.h | 32 /* size of largest OPC field of all the instruction categories: */
35 #define _OPC(cat, opc) (((cat) << NOPC_BITS) | opc)
212 #define opc_cat(opc) ((int)((opc) >> NOPC_BITS))
213 #define opc_op(opc) ((unsigned)((opc) & ((1 << NOPC_BITS) - 1)))
312 uint32_t opc : 4; member in struct:PACKED
418 uint32_t opc : 6; member in struct:PACKED
478 uint32_t opc : 4 member in struct:PACKED
535 uint32_t opc : 6; member in struct:PACKED
584 uint32_t opc : 5; member in struct:PACKED
666 uint32_t opc : 5; member in struct:PACKED::PACKED
[all...] |
| ir3_depth.c | 77 } else if ((is_mad(consumer->opc) || is_madsh(consumer->opc)) &&
140 if (instr->opc == OPC_END)
|
| /external/autotest/client/cros/cellular/ |
| prologix_scpi_driver_test_noautorun.py | 43 self._get_idns_and_verify(instruments=[instr], opc=True)
66 self._get_idns_and_verify(instruments=[instr], opc=True)
152 Test with opc True. OPC= operation complete. Asking this
153 question *OPC? after commands blocks until the command finishes.
158 self._get_idns_and_verify(instruments=scpi_instruments, opc=True)
162 Now with OPC off.
164 self._get_idns_and_verify(instruments=scpi_instruments, opc=False)
180 log.debug("setting opc to %s " % opc_on_stanza)
184 def _get_idns_and_verify(self, instruments, opc=False)
[all...] |
| /external/libunwind/src/ia64/ |
| Gscript.c | 267 enum ia64_script_insn_opcode opc; local
275 opc = IA64_INSN_MOVE;
286 opc = IA64_INSN_MOVE_STACKED_NAT;
288 opc = IA64_INSN_MOVE_STACKED;
296 opc = IA64_INSN_MOVE_NAT;
302 opc = IA64_INSN_MOVE_SCRATCH_NAT;
304 opc = IA64_INSN_MOVE_SCRATCH;
323 opc = IA64_INSN_MOVE_SCRATCH;
333 opc = IA64_INSN_MOVE_NO_NAT;
337 opc = IA64_INSN_MOVE_SCRATCH
521 unsigned long opc, dst; local
[all...] |
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| MallocOverflowSecurityChecker.cpp | 83 BinaryOperatorKind opc = binop->getOpcode(); local
85 if (mulop == nullptr && opc == BO_Mul)
87 if (opc != BO_Mul && opc != BO_Add && opc != BO_Sub && opc != BO_Shl)
95 if (EvaluatesToZero(maxVal, opc))
97 } else if ((opc == BO_Add || opc == BO_Mul) &&
100 if (EvaluatesToZero(maxVal, opc))
[all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| cgen.h | 614 to <arch>-opc.h, or add a hook. */
962 #define CGEN_OPCODE_HANDLERS(opc) (& (opc)->handlers)
966 #define CGEN_OPCODE_SYNTAX(opc) (& (opc)->syntax)
970 #define CGEN_OPCODE_FORMAT(opc) ((opc)->format
[all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-m68hc11.c | 474 struct m68hc11_opcode_def *opc;
478 opc = m68hc11_opcode_defs;
479 if (opc == 0 || m68hc11_nb_opcode_defs == 0)
484 for (i = 0; i < m68hc11_nb_opcode_defs; i++, opc++)
487 opc->opcode->name,
488 opc->nb_modes,
489 opc->min_operands, opc->max_operands, opc->format, opc->used)
473 struct m68hc11_opcode_def *opc; local
608 struct m68hc11_opcode_def *opc = 0; local
1012 struct m68hc11_opcode_def *opc; local
2814 struct m68hc11_opcode_def *opc; local
[all...] |
| /external/libunwind/include/tdep-ia64/ |
| script.h | 36 unsigned int opc; /* see enum ia64_script_insn_opcode */ member in struct:ia64_script_insn
|
