1 /* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12. 2 Copyright (C) 1999-2014 Free Software Foundation, Inc. 3 Written by Stephane Carrez (stcarrez (at) nerim.fr) 4 XGATE and S12X added by James Murray (jsm (at) jsm-net.demon.co.uk) 5 6 This file is part of GAS, the GNU Assembler. 7 8 GAS is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GAS is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GAS; see the file COPYING. If not, write to 20 the Free Software Foundation, 51 Franklin Street - Fifth Floor, 21 Boston, MA 02110-1301, USA. */ 22 23 #include "as.h" 24 #include "safe-ctype.h" 25 #include "subsegs.h" 26 #include "opcode/m68hc11.h" 27 #include "dwarf2dbg.h" 28 #include "elf/m68hc11.h" 29 30 const char comment_chars[] = ";!"; 31 const char line_comment_chars[] = "#*"; 32 const char line_separator_chars[] = ""; 33 34 const char EXP_CHARS[] = "eE"; 35 const char FLT_CHARS[] = "dD"; 36 37 #define STATE_CONDITIONAL_BRANCH (1) 38 #define STATE_PC_RELATIVE (2) 39 #define STATE_INDEXED_OFFSET (3) 40 #define STATE_INDEXED_PCREL (4) 41 #define STATE_XBCC_BRANCH (5) 42 #define STATE_CONDITIONAL_BRANCH_6812 (6) 43 44 #define STATE_BYTE (0) 45 #define STATE_BITS5 (0) 46 #define STATE_WORD (1) 47 #define STATE_BITS9 (1) 48 #define STATE_LONG (2) 49 #define STATE_BITS16 (2) 50 #define STATE_UNDF (3) /* Symbol undefined in pass1 */ 51 52 /* This macro has no side-effects. */ 53 #define ENCODE_RELAX(what,length) (((what) << 2) + (length)) 54 #define RELAX_STATE(s) ((s) >> 2) 55 #define RELAX_LENGTH(s) ((s) & 3) 56 57 #define IS_OPCODE(C1,C2) (((C1) & 0x0FF) == ((C2) & 0x0FF)) 58 59 /* This table describes how you change sizes for the various types of variable 60 size expressions. This version only supports two kinds. */ 61 62 /* The fields are: 63 How far Forward this mode will reach. 64 How far Backward this mode will reach. 65 How many bytes this mode will add to the size of the frag. 66 Which mode to go to if the offset won't fit in this one. */ 67 68 relax_typeS md_relax_table[] = 69 { 70 {1, 1, 0, 0}, /* First entries aren't used. */ 71 {1, 1, 0, 0}, /* For no good reason except. */ 72 {1, 1, 0, 0}, /* that the VAX doesn't either. */ 73 {1, 1, 0, 0}, 74 75 /* Relax for bcc <L>. 76 These insns are translated into b!cc +3 jmp L. */ 77 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD)}, 78 {0, 0, 3, 0}, 79 {1, 1, 0, 0}, 80 {1, 1, 0, 0}, 81 82 /* Relax for bsr <L> and bra <L>. 83 These insns are translated into jsr and jmp. */ 84 {(127), (-128), 0, ENCODE_RELAX (STATE_PC_RELATIVE, STATE_WORD)}, 85 {0, 0, 1, 0}, 86 {1, 1, 0, 0}, 87 {1, 1, 0, 0}, 88 89 /* Relax for indexed offset: 5-bits, 9-bits, 16-bits. */ 90 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS9)}, 91 {(255), (-256), 1, ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS16)}, 92 {0, 0, 2, 0}, 93 {1, 1, 0, 0}, 94 95 /* Relax for PC relative offset: 5-bits, 9-bits, 16-bits. 96 For the 9-bit case, there will be a -1 correction to take into 97 account the new byte that's why the range is -255..256. */ 98 {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_BITS9)}, 99 {(256), (-255), 1, ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_BITS16)}, 100 {0, 0, 2, 0}, 101 {1, 1, 0, 0}, 102 103 /* Relax for dbeq/ibeq/tbeq r,<L>: 104 These insns are translated into db!cc +3 jmp L. */ 105 {(255), (-256), 0, ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_WORD)}, 106 {0, 0, 3, 0}, 107 {1, 1, 0, 0}, 108 {1, 1, 0, 0}, 109 110 /* Relax for bcc <L> on 68HC12. 111 These insns are translated into lbcc <L>. */ 112 {(127), (-128), 0, ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_WORD)}, 113 {0, 0, 2, 0}, 114 {1, 1, 0, 0}, 115 {1, 1, 0, 0}, 116 117 }; 118 119 /* 68HC11 and 68HC12 registers. They are numbered according to the 68HC12. */ 120 typedef enum register_id 121 { 122 REG_NONE = -1, 123 REG_A = 0, 124 REG_B = 1, 125 REG_CCR = 2, 126 REG_D = 4, 127 REG_X = 5, 128 REG_Y = 6, 129 REG_SP = 7, 130 REG_PC = 8, 131 REG_R0 = 0, 132 REG_R1 = 1, 133 REG_R2 = 2, 134 REG_R3 = 3, 135 REG_R4 = 4, 136 REG_R5 = 5, 137 REG_R6 = 6, 138 REG_R7 = 7, 139 REG_SP_XG = 8, 140 REG_PC_XG = 9, 141 REG_CCR_XG = 10 142 } register_id; 143 144 typedef struct operand 145 { 146 expressionS exp; 147 register_id reg1; 148 register_id reg2; 149 int mode; 150 } operand; 151 152 struct m68hc11_opcode_def 153 { 154 long format; 155 int min_operands; 156 int max_operands; 157 int nb_modes; 158 int used; 159 struct m68hc11_opcode *opcode; 160 }; 161 162 static struct m68hc11_opcode_def *m68hc11_opcode_defs = 0; 163 static int m68hc11_nb_opcode_defs = 0; 164 165 typedef struct alias 166 { 167 const char *name; 168 const char *alias; 169 } alias; 170 171 static alias alias_opcodes[] = 172 { 173 {"cpd", "cmpd"}, 174 {"cpx", "cmpx"}, 175 {"cpy", "cmpy"}, 176 {0, 0} 177 }; 178 179 struct m9s12xg_opcode_def 180 { 181 long format; 182 int min_operands; 183 int max_operands; 184 int nb_modes; 185 int used; 186 struct m9s12xg_opcode *opcode; 187 }; 188 189 /* Local functions. */ 190 static register_id reg_name_search (char *); 191 static register_id register_name (void); 192 static int cmp_opcode (struct m68hc11_opcode *, struct m68hc11_opcode *); 193 static char *print_opcode_format (struct m68hc11_opcode *, int); 194 static char *skip_whites (char *); 195 static int check_range (long, int); 196 static void print_opcode_list (void); 197 static void get_default_target (void); 198 static void print_insn_format (char *); 199 static int get_operand (operand *, int, long); 200 static void fixup8 (expressionS *, int, int); 201 static void fixup16 (expressionS *, int, int); 202 static void fixup24 (expressionS *, int, int); 203 static void fixup8_xg (expressionS *, int, int); 204 static unsigned char convert_branch (unsigned char); 205 static char *m68hc11_new_insn (int); 206 static void build_dbranch_insn (struct m68hc11_opcode *, 207 operand *, int, int); 208 static int build_indexed_byte (operand *, int, int); 209 static int build_reg_mode (operand *, int); 210 211 static struct m68hc11_opcode *find (struct m68hc11_opcode_def *, 212 operand *, int); 213 static struct m68hc11_opcode *find_opcode (struct m68hc11_opcode_def *, 214 operand *, int *); 215 static void build_jump_insn (struct m68hc11_opcode *, operand *, int, int); 216 static void build_insn_xg (struct m68hc11_opcode *, operand *, int); 217 static void build_insn (struct m68hc11_opcode *, operand *, int); 218 static int relaxable_symbol (symbolS *); 219 220 /* Pseudo op to indicate a relax group. */ 221 static void s_m68hc11_relax (int); 222 223 /* Pseudo op to control the ELF flags. */ 224 static void s_m68hc11_mode (int); 225 226 /* Process directives specified via pseudo ops. */ 227 static void s_m68hc11_parse_pseudo_instruction (int); 228 229 /* Mark the symbols with STO_M68HC12_FAR to indicate the functions 230 are using 'rtc' for returning. It is necessary to use 'call' 231 to invoke them. This is also used by the debugger to correctly 232 find the stack frame. */ 233 static void s_m68hc11_mark_symbol (int); 234 235 /* Controls whether relative branches can be turned into long branches. 236 When the relative offset is too large, the insn are changed: 237 bra -> jmp 238 bsr -> jsr 239 bcc -> b!cc +3 240 jmp L 241 dbcc -> db!cc +3 242 jmp L 243 244 Setting the flag forbidds this. */ 245 static short flag_fixed_branches = 0; 246 247 /* Force to use long jumps (absolute) instead of relative branches. */ 248 static short flag_force_long_jumps = 0; 249 250 /* Change the direct addressing mode into an absolute addressing mode 251 when the insn does not support direct addressing. 252 For example, "clr *ZD0" is normally not possible and is changed 253 into "clr ZDO". */ 254 static short flag_strict_direct_addressing = 1; 255 256 /* When an opcode has invalid operand, print out the syntax of the opcode 257 to stderr. */ 258 static short flag_print_insn_syntax = 0; 259 260 /* Dumps the list of instructions with syntax and then exit: 261 1 -> Only dumps the list (sorted by name) 262 2 -> Generate an example (or test) that can be compiled. */ 263 static short flag_print_opcodes = 0; 264 265 /* Opcode hash table. */ 266 static struct hash_control *m68hc11_hash; 267 268 /* Current cpu (either cpu6811 or cpu6812). This is determined automagically 269 by 'get_default_target' by looking at default BFD vector. This is overridden 270 with the -m<cpu> option. */ 271 static int current_architecture = 0; 272 273 /* Default cpu determined by 'get_default_target'. */ 274 static const char *default_cpu; 275 276 /* Number of opcodes in the sorted table (filtered by current cpu). */ 277 static int num_opcodes; 278 279 /* The opcodes sorted by name and filtered by current cpu. */ 280 static struct m68hc11_opcode *m68hc11_sorted_opcodes; 281 282 /* ELF flags to set in the output file header. */ 283 static int elf_flags = E_M68HC11_F64; 284 285 /* These are the machine dependent pseudo-ops. These are included so 286 the assembler can work on the output from the SUN C compiler, which 287 generates these. */ 288 289 /* This table describes all the machine specific pseudo-ops the assembler 290 has to support. The fields are: 291 pseudo-op name without dot 292 function to call to execute this pseudo-op 293 Integer arg to pass to the function. */ 294 const pseudo_typeS md_pseudo_table[] = 295 { 296 /* The following pseudo-ops are supported for MRI compatibility. */ 297 {"fcb", cons, 1}, 298 {"fdb", cons, 2}, 299 {"fqb", cons, 4}, 300 {"fcc", stringer, 8 + 1}, 301 {"rmb", s_space, 0}, 302 303 /* Motorola ALIS. */ 304 {"xrefb", s_ignore, 0}, /* Same as xref */ 305 306 /* Gcc driven relaxation. */ 307 {"relax", s_m68hc11_relax, 0}, 308 309 /* .mode instruction (ala SH). */ 310 {"mode", s_m68hc11_mode, 0}, 311 312 /* .far instruction. */ 313 {"far", s_m68hc11_mark_symbol, STO_M68HC12_FAR}, 314 315 /* .interrupt instruction. */ 316 {"interrupt", s_m68hc11_mark_symbol, STO_M68HC12_INTERRUPT}, 317 318 /* .nobankwarning instruction. */ 319 {"nobankwarning", s_m68hc11_parse_pseudo_instruction, E_M68HC11_NO_BANK_WARNING}, 320 321 {0, 0, 0} 322 }; 323 324 /* Options and initialization. */ 326 327 const char *md_shortopts = "Sm:"; 328 329 struct option md_longopts[] = 330 { 331 #define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE) 332 {"force-long-branches", no_argument, NULL, OPTION_FORCE_LONG_BRANCH}, 333 {"force-long-branchs", no_argument, NULL, OPTION_FORCE_LONG_BRANCH}, /* Misspelt version kept for backwards compatibility. */ 334 335 #define OPTION_SHORT_BRANCHES (OPTION_MD_BASE + 1) 336 {"short-branches", no_argument, NULL, OPTION_SHORT_BRANCHES}, 337 {"short-branchs", no_argument, NULL, OPTION_SHORT_BRANCHES}, /* Misspelt version kept for backwards compatibility. */ 338 339 #define OPTION_STRICT_DIRECT_MODE (OPTION_MD_BASE + 2) 340 {"strict-direct-mode", no_argument, NULL, OPTION_STRICT_DIRECT_MODE}, 341 342 #define OPTION_PRINT_INSN_SYNTAX (OPTION_MD_BASE + 3) 343 {"print-insn-syntax", no_argument, NULL, OPTION_PRINT_INSN_SYNTAX}, 344 345 #define OPTION_PRINT_OPCODES (OPTION_MD_BASE + 4) 346 {"print-opcodes", no_argument, NULL, OPTION_PRINT_OPCODES}, 347 348 #define OPTION_GENERATE_EXAMPLE (OPTION_MD_BASE + 5) 349 {"generate-example", no_argument, NULL, OPTION_GENERATE_EXAMPLE}, 350 351 #define OPTION_MSHORT (OPTION_MD_BASE + 6) 352 {"mshort", no_argument, NULL, OPTION_MSHORT}, 353 354 #define OPTION_MLONG (OPTION_MD_BASE + 7) 355 {"mlong", no_argument, NULL, OPTION_MLONG}, 356 357 #define OPTION_MSHORT_DOUBLE (OPTION_MD_BASE + 8) 358 {"mshort-double", no_argument, NULL, OPTION_MSHORT_DOUBLE}, 359 360 #define OPTION_MLONG_DOUBLE (OPTION_MD_BASE + 9) 361 {"mlong-double", no_argument, NULL, OPTION_MLONG_DOUBLE}, 362 363 #define OPTION_XGATE_RAMOFFSET (OPTION_MD_BASE + 10) 364 {"xgate-ramoffset", no_argument, NULL, OPTION_XGATE_RAMOFFSET}, 365 366 {NULL, no_argument, NULL, 0} 367 }; 368 size_t md_longopts_size = sizeof (md_longopts); 369 370 /* Get the target cpu for the assembler. This is based on the configure 371 options and on the -m68hc11/-m68hc12 option. If no option is specified, 372 we must get the default. */ 373 const char * 374 m68hc11_arch_format (void) 375 { 376 get_default_target (); 377 if (current_architecture & cpu6811) 378 return "elf32-m68hc11"; 379 else 380 return "elf32-m68hc12"; 381 } 382 383 enum bfd_architecture 384 m68hc11_arch (void) 385 { 386 get_default_target (); 387 if (current_architecture & cpu6811) 388 return bfd_arch_m68hc11; 389 else 390 return bfd_arch_m68hc12; 391 } 392 393 int 394 m68hc11_mach (void) 395 { 396 return 0; 397 } 398 399 /* Listing header selected according to cpu. */ 400 const char * 401 m68hc11_listing_header (void) 402 { 403 if (current_architecture & cpu6811) 404 return "M68HC11 GAS "; 405 else if (current_architecture & cpuxgate) 406 return "XGATE GAS "; 407 else if (current_architecture & cpu9s12x) 408 return "S12X GAS "; 409 else 410 return "M68HC12 GAS "; 411 } 412 413 void 414 md_show_usage (FILE *stream) 415 { 416 get_default_target (); 417 fprintf (stream, _("\ 418 Motorola 68HC11/68HC12/68HCS12 options:\n\ 419 -m68hc11 | -m68hc12 |\n\ 420 -m68hcs12 | -mm9s12x |\n\ 421 -mm9s12xg specify the processor [default %s]\n\ 422 -mshort use 16-bit int ABI (default)\n\ 423 -mlong use 32-bit int ABI\n\ 424 -mshort-double use 32-bit double ABI\n\ 425 -mlong-double use 64-bit double ABI (default)\n\ 426 --force-long-branches always turn relative branches into absolute ones\n\ 427 -S,--short-branches do not turn relative branches into absolute ones\n\ 428 when the offset is out of range\n\ 429 --strict-direct-mode do not turn the direct mode into extended mode\n\ 430 when the instruction does not support direct mode\n\ 431 --print-insn-syntax print the syntax of instruction in case of error\n\ 432 --print-opcodes print the list of instructions with syntax\n\ 433 --xgate-ramoffset offset ram addresses by 0xc000\n\ 434 --generate-example generate an example of each instruction\n\ 435 (used for testing)\n"), default_cpu); 436 437 } 438 439 /* Try to identify the default target based on the BFD library. */ 440 static void 441 get_default_target (void) 442 { 443 const bfd_target *target; 444 bfd abfd; 445 446 if (current_architecture != 0) 447 return; 448 449 default_cpu = "unknown"; 450 target = bfd_find_target (0, &abfd); 451 if (target && target->name) 452 { 453 if (strcmp (target->name, "elf32-m68hc12") == 0) 454 { 455 current_architecture = cpu6812; 456 default_cpu = "m68hc12"; 457 } 458 else if (strcmp (target->name, "elf32-m68hc11") == 0) 459 { 460 current_architecture = cpu6811; 461 default_cpu = "m68hc11"; 462 } 463 else 464 { 465 as_bad (_("Default target `%s' is not supported."), target->name); 466 } 467 } 468 } 469 470 void 471 m68hc11_print_statistics (FILE *file) 472 { 473 int i; 474 struct m68hc11_opcode_def *opc; 475 476 hash_print_statistics (file, "opcode table", m68hc11_hash); 477 478 opc = m68hc11_opcode_defs; 479 if (opc == 0 || m68hc11_nb_opcode_defs == 0) 480 return; 481 482 /* Dump the opcode statistics table. */ 483 fprintf (file, _("Name # Modes Min ops Max ops Modes mask # Used\n")); 484 for (i = 0; i < m68hc11_nb_opcode_defs; i++, opc++) 485 { 486 fprintf (file, "%-7.7s %5d %7d %7d 0x%08lx %7d\n", 487 opc->opcode->name, 488 opc->nb_modes, 489 opc->min_operands, opc->max_operands, opc->format, opc->used); 490 } 491 } 492 493 int 494 md_parse_option (int c, char *arg) 495 { 496 get_default_target (); 497 switch (c) 498 { 499 /* -S means keep external to 2 bit offset rather than 16 bit one. */ 500 case OPTION_SHORT_BRANCHES: 501 case 'S': 502 flag_fixed_branches = 1; 503 break; 504 505 case OPTION_FORCE_LONG_BRANCH: 506 flag_force_long_jumps = 1; 507 break; 508 509 case OPTION_PRINT_INSN_SYNTAX: 510 flag_print_insn_syntax = 1; 511 break; 512 513 case OPTION_PRINT_OPCODES: 514 flag_print_opcodes = 1; 515 break; 516 517 case OPTION_STRICT_DIRECT_MODE: 518 flag_strict_direct_addressing = 0; 519 break; 520 521 case OPTION_GENERATE_EXAMPLE: 522 flag_print_opcodes = 2; 523 break; 524 525 case OPTION_MSHORT: 526 elf_flags &= ~E_M68HC11_I32; 527 break; 528 529 case OPTION_MLONG: 530 elf_flags |= E_M68HC11_I32; 531 break; 532 533 case OPTION_MSHORT_DOUBLE: 534 elf_flags &= ~E_M68HC11_F64; 535 break; 536 537 case OPTION_MLONG_DOUBLE: 538 elf_flags |= E_M68HC11_F64; 539 break; 540 541 case OPTION_XGATE_RAMOFFSET: 542 elf_flags |= E_M68HC11_XGATE_RAMOFFSET; 543 break; 544 545 case 'm': 546 if ((strcasecmp (arg, "68hc11") == 0) 547 || (strcasecmp (arg, "m68hc11") == 0)) 548 current_architecture = cpu6811; 549 else if ((strcasecmp (arg, "68hc12") == 0) 550 || (strcasecmp (arg, "m68hc12") == 0)) 551 current_architecture = cpu6812; 552 else if ((strcasecmp (arg, "68hcs12") == 0) 553 || (strcasecmp (arg, "m68hcs12") == 0)) 554 current_architecture = cpu6812 | cpu6812s; 555 else if (strcasecmp (arg, "m9s12x") == 0) 556 current_architecture = cpu6812 | cpu6812s | cpu9s12x; 557 else if ((strcasecmp (arg, "m9s12xg") == 0) 558 || (strcasecmp (arg, "xgate") == 0)) 559 /* xgate for backwards compatability */ 560 current_architecture = cpuxgate; 561 else 562 as_bad (_("Option `%s' is not recognized."), arg); 563 break; 564 565 default: 566 return 0; 567 } 568 569 return 1; 570 } 571 572 symbolS * 574 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 575 { 576 return 0; 577 } 578 579 char * 580 md_atof (int type, char *litP, int *sizeP) 581 { 582 return ieee_md_atof (type, litP, sizeP, TRUE); 583 } 584 585 valueT 586 md_section_align (asection *seg, valueT addr) 587 { 588 int align = bfd_get_section_alignment (stdoutput, seg); 589 return ((addr + (1 << align) - 1) & (-1 << align)); 590 } 591 592 static int 593 cmp_opcode (struct m68hc11_opcode *op1, struct m68hc11_opcode *op2) 594 { 595 return strcmp (op1->name, op2->name); 596 } 597 598 #define IS_CALL_SYMBOL(MODE) \ 599 (((MODE) & (M6812_OP_PAGE|M6811_OP_IND16)) \ 600 == ((M6812_OP_PAGE|M6811_OP_IND16))) 601 602 /* Initialize the assembler. Create the opcode hash table 603 (sorted on the names) with the M6811 opcode table 604 (from opcode library). */ 605 void 606 md_begin (void) 607 { 608 char *prev_name = ""; 609 struct m68hc11_opcode *opcodes; 610 struct m68hc11_opcode_def *opc = 0; 611 int i, j; 612 613 get_default_target (); 614 615 m68hc11_hash = hash_new (); 616 617 /* Get a writable copy of the opcode table and sort it on the names. */ 618 opcodes = (struct m68hc11_opcode *) xmalloc (m68hc11_num_opcodes * 619 sizeof (struct 620 m68hc11_opcode)); 621 m68hc11_sorted_opcodes = opcodes; 622 num_opcodes = 0; 623 for (i = 0; i < m68hc11_num_opcodes; i++) 624 { 625 if (m68hc11_opcodes[i].arch & current_architecture) 626 { 627 opcodes[num_opcodes] = m68hc11_opcodes[i]; 628 if (opcodes[num_opcodes].name[0] == 'b' 629 && opcodes[num_opcodes].format & M6811_OP_JUMP_REL 630 && !(opcodes[num_opcodes].format & M6811_OP_BITMASK)) 631 { 632 num_opcodes++; 633 opcodes[num_opcodes] = m68hc11_opcodes[i]; 634 } 635 num_opcodes++; 636 for (j = 0; alias_opcodes[j].name != 0; j++) 637 if (strcmp (m68hc11_opcodes[i].name, alias_opcodes[j].name) == 0) 638 { 639 opcodes[num_opcodes] = m68hc11_opcodes[i]; 640 opcodes[num_opcodes].name = alias_opcodes[j].alias; 641 num_opcodes++; 642 break; 643 } 644 } 645 } 646 qsort (opcodes, num_opcodes, sizeof (struct m68hc11_opcode), 647 (int (*) (const void*, const void*)) cmp_opcode); 648 649 opc = (struct m68hc11_opcode_def *) 650 xmalloc (num_opcodes * sizeof (struct m68hc11_opcode_def)); 651 m68hc11_opcode_defs = opc--; 652 653 /* Insert unique names into hash table. The M6811 instruction set 654 has several identical opcode names that have different opcodes based 655 on the operands. This hash table then provides a quick index to 656 the first opcode with a particular name in the opcode table. */ 657 for (i = 0; i < num_opcodes; i++, opcodes++) 658 { 659 int expect; 660 661 if (strcmp (prev_name, opcodes->name)) 662 { 663 prev_name = (char *) opcodes->name; 664 665 opc++; 666 opc->format = 0; 667 opc->min_operands = 100; 668 opc->max_operands = 0; 669 opc->nb_modes = 0; 670 opc->opcode = opcodes; 671 opc->used = 0; 672 hash_insert (m68hc11_hash, opcodes->name, opc); 673 } 674 opc->nb_modes++; 675 opc->format |= opcodes->format; 676 677 /* See how many operands this opcode needs. */ 678 expect = 0; 679 if (opcodes->arch == cpuxgate) 680 { 681 if (opcodes->format & (M68XG_OP_IMM3 | M68XG_OP_R | M68XG_OP_REL9 682 | M68XG_OP_REL10 )) 683 expect = 1; 684 else if (opcodes->format & (M68XG_OP_R_R | M68XG_OP_R_IMM4 685 | M68XG_OP_R_IMM8 | M68XG_OP_R_IMM8)) 686 expect = 2; 687 else if (opcodes->format & (M68XG_OP_R_R_R | M68XG_OP_R_R_OFFS5 688 | M68XG_OP_RD_RB_RI | M68XG_OP_RD_RB_RIp 689 | M68XG_OP_RD_RB_mRI)) 690 expect = 3; 691 } 692 else 693 { 694 if (opcodes->format & M6811_OP_MASK) 695 expect++; 696 if (opcodes->format & M6811_OP_BITMASK) 697 expect++; 698 if (opcodes->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) 699 expect++; 700 if (opcodes->format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2)) 701 expect++; 702 /* Special case for call instruction. */ 703 if ((opcodes->format & M6812_OP_PAGE) 704 && !(opcodes->format & M6811_OP_IND16)) 705 expect++; 706 } 707 708 if (expect < opc->min_operands) 709 opc->min_operands = expect; 710 if (IS_CALL_SYMBOL (opcodes->format)) 711 expect++; 712 if (expect > opc->max_operands) 713 opc->max_operands = expect; 714 } 715 opc++; 716 m68hc11_nb_opcode_defs = opc - m68hc11_opcode_defs; 717 718 if (flag_print_opcodes) 719 { 720 print_opcode_list (); 721 exit (EXIT_SUCCESS); 722 } 723 } 724 725 void 726 m68hc11_init_after_args (void) 727 { 728 } 729 730 /* Builtin help. */ 732 733 /* Return a string that represents the operand format for the instruction. 734 When example is true, this generates an example of operand. This is used 735 to give an example and also to generate a test. */ 736 737 static char * 738 print_opcode_format (struct m68hc11_opcode *opcode, int example) 739 { 740 static char buf[128]; 741 int format = opcode->format; 742 char *p; 743 744 p = buf; 745 buf[0] = 0; 746 747 if (current_architecture == cpuxgate) 748 { 749 if (format & M68XG_OP_IMM3) 750 { 751 if (example) 752 sprintf (p, "#%d", rand () & 0x007); 753 else 754 strcpy (p, _("imm3")); 755 p = &p[strlen (p)]; 756 } 757 else if (format & M68XG_OP_R) 758 { 759 if (example) 760 sprintf (p, "R%d", rand () & 0x07); 761 else 762 strcpy (p, _("RD")); 763 p = &p[strlen (p)]; 764 } 765 else if (format & M68XG_OP_R_R) 766 { 767 if (example) 768 sprintf (p, "R%d,R%d", rand () & 0x07, rand () & 0x07); 769 else 770 strcpy (p, _("RD,RS")); 771 p = &p[strlen (p)]; 772 } 773 else if (format & M68XG_OP_R_IMM4) 774 { 775 if (example) 776 sprintf (p, "R%d,#%d", rand () & 0x07, rand () & 0x0f); 777 else 778 strcpy (p, _("RI, #imm4")); 779 p = &p[strlen (p)]; 780 } 781 else if (format & M68XG_OP_R_R_R) 782 { 783 if (example) 784 sprintf (p, "R%d,R%d,R%d", rand () & 0x07, rand () & 0x07, rand () & 0x07); 785 else 786 strcpy (p, "RD,RS1,RS2"); 787 p = &p[strlen (p)]; 788 } 789 else if (format & M68XG_OP_REL9) 790 { 791 if (example) 792 sprintf (p, "%d", rand () & 0x1FF); 793 else 794 strcpy (p, "<rel9>"); 795 p = &p[strlen (p)]; 796 } 797 else if (format & M68XG_OP_REL10) 798 { 799 if (example) 800 sprintf (p, "%d", rand () & 0x3FF); 801 else 802 strcpy (p, "<rel10>"); 803 p = &p[strlen (p)]; 804 } 805 else if (format & M68XG_OP_R_R_OFFS5) 806 { 807 if (example) 808 sprintf (p, "R%d, (R%d, #0x%x)", rand () & 0x07, rand () & 0x07, rand () & 0x1f); 809 else 810 strcpy (p, _("RD, (RI,#offs5)")); 811 p = &p[strlen (p)]; 812 } 813 else if (format & M68XG_OP_RD_RB_RI) 814 { 815 if (example) 816 sprintf (p, "R%d, (R%d, R%d)", rand () & 0x07, rand () & 0x07, rand () & 0x07); 817 else 818 strcpy (p, "RD, (RB, RI)"); 819 p = &p[strlen (p)]; 820 } 821 else if (format & M68XG_OP_RD_RB_RIp) 822 { 823 if (example) 824 sprintf (p, "R%d, (R%d, R%d+)", rand () & 0x07, rand () & 0x07, rand () & 0x07); 825 else 826 strcpy (p, "RD, (RB, RI+)"); 827 p = &p[strlen (p)]; 828 } 829 else if (format & M68XG_OP_RD_RB_mRI) 830 { 831 if (example) 832 sprintf (p, "R%d, (R%d, -R%d)", rand () & 0x07, rand () & 0x07, rand () & 0x07); 833 else 834 strcpy (p, "RD, (RB, -RI)"); 835 p = &p[strlen (p)]; 836 } 837 else if (format & M68XG_OP_R_IMM8) 838 { 839 if (example) 840 sprintf (p, "R%d, #0x%x", rand () & 0x07, rand () & 0xff); 841 else 842 strcpy (p, "RD, #imm8"); 843 p = &p[strlen (p)]; 844 } 845 else if (format & M68XG_OP_R_IMM16) 846 { 847 if (example) 848 sprintf (p, "R%d, #0x%x", rand () & 0x07, rand () & 0xffff); 849 else 850 strcpy (p, "RD, #imm16"); 851 p = &p[strlen (p)]; 852 } 853 } 854 else 855 { 856 857 if (format & M6811_OP_IMM8) 858 { 859 if (example) 860 sprintf (p, "#%d", rand () & 0x0FF); 861 else 862 strcpy (p, _("#<imm8>")); 863 p = &p[strlen (p)]; 864 } 865 866 if (format & M6811_OP_IMM16) 867 { 868 if (example) 869 sprintf (p, "#%d", rand () & 0x0FFFF); 870 else 871 strcpy (p, _("#<imm16>")); 872 p = &p[strlen (p)]; 873 } 874 875 if (format & M6811_OP_IX) 876 { 877 if (example) 878 sprintf (p, "%d,X", rand () & 0x0FF); 879 else 880 strcpy (p, _("<imm8>,X")); 881 p = &p[strlen (p)]; 882 } 883 884 if (format & M6811_OP_IY) 885 { 886 if (example) 887 sprintf (p, "%d,X", rand () & 0x0FF); 888 else 889 strcpy (p, _("<imm8>,X")); 890 p = &p[strlen (p)]; 891 } 892 893 if (format & M6812_OP_IDX) 894 { 895 if (example) 896 sprintf (p, "%d,X", rand () & 0x0FF); 897 else 898 strcpy (p, "n,r"); 899 p = &p[strlen (p)]; 900 } 901 902 if (format & M6812_OP_PAGE) 903 { 904 if (example) 905 sprintf (p, ", %d", rand () & 0x0FF); 906 else 907 strcpy (p, ", <page>"); 908 p = &p[strlen (p)]; 909 } 910 911 if (format & M6811_OP_DIRECT) 912 { 913 if (example) 914 sprintf (p, "*Z%d", rand () & 0x0FF); 915 else 916 strcpy (p, _("*<abs8>")); 917 p = &p[strlen (p)]; 918 } 919 920 if (format & M6811_OP_BITMASK) 921 { 922 if (buf[0]) 923 *p++ = ' '; 924 925 if (example) 926 sprintf (p, "#$%02x", rand () & 0x0FF); 927 else 928 strcpy (p, _("#<mask>")); 929 930 p = &p[strlen (p)]; 931 if (format & M6811_OP_JUMP_REL) 932 *p++ = ' '; 933 } 934 935 if (format & M6811_OP_IND16) 936 { 937 if (example) 938 sprintf (p, _("symbol%d"), rand () & 0x0FF); 939 else 940 strcpy (p, _("<abs>")); 941 942 p = &p[strlen (p)]; 943 } 944 945 if (format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) 946 { 947 if (example) 948 { 949 if (format & M6811_OP_BITMASK) 950 { 951 sprintf (p, ".+%d", rand () & 0x7F); 952 } 953 else 954 { 955 sprintf (p, "L%d", rand () & 0x0FF); 956 } 957 } 958 else 959 strcpy (p, _("<label>")); 960 } 961 } 962 return buf; 963 } 964 965 /* Prints the list of instructions with the possible operands. */ 966 static void 967 print_opcode_list (void) 968 { 969 int i; 970 char *prev_name = ""; 971 struct m68hc11_opcode *opcodes; 972 int example = flag_print_opcodes == 2; 973 974 if (example) 975 printf (_("# Example of `%s' instructions\n\t.sect .text\n_start:\n"), 976 default_cpu); 977 978 opcodes = m68hc11_sorted_opcodes; 979 980 /* Walk the list sorted on names (by md_begin). We only report 981 one instruction per line, and we collect the different operand 982 formats. */ 983 for (i = 0; i < num_opcodes; i++, opcodes++) 984 { 985 char *fmt = print_opcode_format (opcodes, example); 986 987 if (example) 988 { 989 printf ("L%d:\t", i); 990 printf ("%s %s\n", opcodes->name, fmt); 991 } 992 else 993 { 994 if (strcmp (prev_name, opcodes->name)) 995 { 996 if (i > 0) 997 printf ("\n"); 998 999 printf ("%-5.5s ", opcodes->name); 1000 prev_name = (char *) opcodes->name; 1001 } 1002 if (fmt[0]) 1003 printf (" [%s]", fmt); 1004 } 1005 } 1006 printf ("\n"); 1007 } 1008 1009 /* Print the instruction format. This operation is called when some 1010 instruction is not correct. Instruction format is printed as an 1011 error message. */ 1012 static void 1013 print_insn_format (char *name) 1014 { 1015 struct m68hc11_opcode_def *opc; 1016 struct m68hc11_opcode *opcode; 1017 char buf[128]; 1018 1019 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name); 1020 if (opc == NULL) 1021 { 1022 as_bad (_("Instruction `%s' is not recognized."), name); 1023 return; 1024 } 1025 opcode = opc->opcode; 1026 1027 as_bad (_("Instruction formats for `%s':"), name); 1028 do 1029 { 1030 char *fmt; 1031 1032 fmt = print_opcode_format (opcode, 0); 1033 sprintf (buf, "\t%-5.5s %s", opcode->name, fmt); 1034 1035 as_bad ("%s", buf); 1036 opcode++; 1037 } 1038 while (strcmp (opcode->name, name) == 0); 1039 } 1040 1041 /* Analysis of 68HC11 and 68HC12 operands. */ 1043 1044 /* reg_name_search() finds the register number given its name. 1045 Returns the register number or REG_NONE on failure. */ 1046 static register_id 1047 reg_name_search (char *name) 1048 { 1049 if (strcasecmp (name, "x") == 0 || strcasecmp (name, "ix") == 0) 1050 return REG_X; 1051 if (strcasecmp (name, "y") == 0 || strcasecmp (name, "iy") == 0) 1052 return REG_Y; 1053 if (strcasecmp (name, "a") == 0) 1054 return REG_A; 1055 if (strcasecmp (name, "b") == 0) 1056 return REG_B; 1057 if (strcasecmp (name, "d") == 0) 1058 return REG_D; 1059 if (strcasecmp (name, "sp") == 0) 1060 return REG_SP; 1061 if (strcasecmp (name, "pc") == 0) 1062 return REG_PC; 1063 if (strcasecmp (name, "ccr") == 0) 1064 return REG_CCR; 1065 /* XGATE */ 1066 if (strcasecmp (name, "r0") == 0) 1067 return REG_R0; 1068 if (strcasecmp (name, "r1") == 0) 1069 return REG_R1; 1070 if (strcasecmp (name, "r2") == 0) 1071 return REG_R2; 1072 if (strcasecmp (name, "r3") == 0) 1073 return REG_R3; 1074 if (strcasecmp (name, "r4") == 0) 1075 return REG_R4; 1076 if (strcasecmp (name, "r5") == 0) 1077 return REG_R5; 1078 if (strcasecmp (name, "r6") == 0) 1079 return REG_R6; 1080 if (strcasecmp (name, "r7") == 0) 1081 return REG_R7; 1082 if (strcasecmp (name, "sp") == 0) 1083 return REG_SP_XG; 1084 if (strcasecmp (name, "pc") == 0) 1085 return REG_PC_XG; 1086 if (strcasecmp (name, "ccr") == 0) 1087 return REG_CCR_XG; 1088 return REG_NONE; 1089 } 1090 1091 static char * 1092 skip_whites (char *p) 1093 { 1094 while (*p == ' ' || *p == '\t') 1095 p++; 1096 1097 return p; 1098 } 1099 1100 /* Check the string at input_line_pointer 1101 to see if it is a valid register name. */ 1102 static register_id 1103 register_name (void) 1104 { 1105 register_id reg_number; 1106 char c, *p = input_line_pointer; 1107 1108 if (!is_name_beginner (*p++)) 1109 return REG_NONE; 1110 1111 while (is_part_of_name (*p++)) 1112 continue; 1113 1114 c = *--p; 1115 if (c) 1116 *p++ = 0; 1117 1118 /* Look to see if it's in the register table. */ 1119 reg_number = reg_name_search (input_line_pointer); 1120 if (reg_number != REG_NONE) 1121 { 1122 if (c) 1123 *--p = c; 1124 1125 input_line_pointer = p; 1126 return reg_number; 1127 } 1128 if (c) 1129 *--p = c; 1130 1131 return reg_number; 1132 } 1133 #define M6811_OP_CALL_ADDR 0x00800000 1134 #define M6811_OP_PAGE_ADDR 0x04000000 1135 1136 /* Parse a string of operands and return an array of expressions. 1137 1138 Operand mode[0] mode[1] exp[0] exp[1] 1139 #n M6811_OP_IMM16 - O_* 1140 *<exp> M6811_OP_DIRECT - O_* 1141 .{+-}<exp> M6811_OP_JUMP_REL - O_* 1142 <exp> M6811_OP_IND16 - O_* 1143 ,r N,r M6812_OP_IDX M6812_OP_REG O_constant O_register 1144 n,-r M6812_PRE_DEC M6812_OP_REG O_constant O_register 1145 n,+r M6812_PRE_INC " " 1146 n,r- M6812_POST_DEC " " 1147 n,r+ M6812_POST_INC " " 1148 A,r B,r D,r M6811_OP_REG M6812_OP_REG O_register O_register 1149 [D,r] M6811_OP_D_IDX M6812_OP_REG O_register O_register 1150 [n,r] M6811_OP_D_IDX_2 M6812_OP_REG O_constant O_register */ 1151 static int 1152 get_operand (operand *oper, int which, long opmode) 1153 { 1154 char *p = input_line_pointer; 1155 int mode; 1156 register_id reg; 1157 1158 oper->exp.X_op = O_absent; 1159 oper->reg1 = REG_NONE; 1160 oper->reg2 = REG_NONE; 1161 mode = M6811_OP_NONE; 1162 1163 p = skip_whites (p); 1164 1165 if (*p == 0 || *p == '\n' || *p == '\r') 1166 { 1167 input_line_pointer = p; 1168 return 0; 1169 } 1170 1171 if (*p == '*' && (opmode & (M6811_OP_DIRECT | M6811_OP_IND16))) 1172 { 1173 mode = M6811_OP_DIRECT; 1174 p++; 1175 } 1176 else if (*p == '#') 1177 { 1178 if (!(opmode & (M6811_OP_IMM8 | M6811_OP_IMM16 | M6811_OP_BITMASK))) 1179 { 1180 as_bad (_("Immediate operand is not allowed for operand %d."), 1181 which); 1182 return -1; 1183 } 1184 1185 mode = M6811_OP_IMM16; 1186 p++; 1187 if (strncmp (p, "%hi", 3) == 0) 1188 { 1189 p += 3; 1190 mode |= M6811_OP_HIGH_ADDR; 1191 } 1192 else if (strncmp (p, "%lo", 3) == 0) 1193 { 1194 p += 3; 1195 mode |= M6811_OP_LOW_ADDR; 1196 } 1197 /* %page modifier is used to obtain only the page number 1198 of the address of a function. */ 1199 else if (strncmp (p, "%page", 5) == 0) 1200 { 1201 p += 5; 1202 mode |= M6811_OP_PAGE_ADDR; 1203 } 1204 1205 /* %addr modifier is used to obtain the physical address part 1206 of the function (16-bit). For 68HC12 the function will be 1207 mapped in the 16K window at 0x8000 and the value will be 1208 within that window (although the function address may not fit 1209 in 16-bit). See bfd/elf32-m68hc12.c for the translation. */ 1210 else if (strncmp (p, "%addr", 5) == 0) 1211 { 1212 p += 5; 1213 mode |= M6811_OP_CALL_ADDR; 1214 } 1215 } 1216 else if (*p == '.' && (p[1] == '+' || p[1] == '-')) 1217 { 1218 p++; 1219 mode = M6811_OP_JUMP_REL; 1220 } 1221 else if (*p == '[') 1222 { 1223 if (current_architecture & cpu6811) 1224 as_bad (_("Indirect indexed addressing is not valid for 68HC11.")); 1225 1226 p++; 1227 mode = M6812_OP_D_IDX; 1228 p = skip_whites (p); 1229 } 1230 else if (*p == ',') /* Special handling of ,x and ,y. */ 1231 { 1232 p++; 1233 input_line_pointer = p; 1234 1235 reg = register_name (); 1236 if (reg != REG_NONE) 1237 { 1238 oper->reg1 = reg; 1239 oper->exp.X_op = O_constant; 1240 oper->exp.X_add_number = 0; 1241 oper->mode = M6812_OP_IDX; 1242 return 1; 1243 } 1244 as_bad (_("Spurious `,' or bad indirect register addressing mode.")); 1245 return -1; 1246 } 1247 /* Handle 68HC12 page specification in 'call foo,%page(bar)'. */ 1248 else if ((opmode & M6812_OP_PAGE) && strncmp (p, "%page", 5) == 0) 1249 { 1250 p += 5; 1251 mode = M6811_OP_PAGE_ADDR | M6812_OP_PAGE | M6811_OP_IND16; 1252 } 1253 input_line_pointer = p; 1254 1255 if (mode == M6811_OP_NONE || mode == M6812_OP_D_IDX) 1256 reg = register_name (); 1257 else 1258 reg = REG_NONE; 1259 1260 if (reg != REG_NONE) 1261 { 1262 p = skip_whites (input_line_pointer); 1263 if (*p == ']' && mode == M6812_OP_D_IDX) 1264 { 1265 as_bad 1266 (_("Missing second register or offset for indexed-indirect mode.")); 1267 return -1; 1268 } 1269 1270 oper->reg1 = reg; 1271 oper->mode = mode | M6812_OP_REG; 1272 if (*p != ',') 1273 { 1274 if (mode == M6812_OP_D_IDX) 1275 { 1276 as_bad (_("Missing second register for indexed-indirect mode.")); 1277 return -1; 1278 } 1279 return 1; 1280 } 1281 1282 p++; 1283 input_line_pointer = p; 1284 reg = register_name (); 1285 if (reg != REG_NONE) 1286 { 1287 p = skip_whites (input_line_pointer); 1288 if (mode == M6812_OP_D_IDX) 1289 { 1290 if (*p != ']') 1291 { 1292 as_bad (_("Missing `]' to close indexed-indirect mode.")); 1293 return -1; 1294 } 1295 p++; 1296 oper->mode = M6812_OP_D_IDX; 1297 } 1298 input_line_pointer = p; 1299 1300 oper->reg2 = reg; 1301 return 1; 1302 } 1303 return 1; 1304 } 1305 1306 /* In MRI mode, isolate the operand because we can't distinguish 1307 operands from comments. */ 1308 if (flag_mri) 1309 { 1310 char c = 0; 1311 1312 p = skip_whites (p); 1313 while (*p && *p != ' ' && *p != '\t') 1314 p++; 1315 1316 if (*p) 1317 { 1318 c = *p; 1319 *p = 0; 1320 } 1321 1322 /* Parse as an expression. */ 1323 expression (&oper->exp); 1324 1325 if (c) 1326 { 1327 *p = c; 1328 } 1329 } 1330 else 1331 { 1332 expression (&oper->exp); 1333 } 1334 1335 if (oper->exp.X_op == O_illegal) 1336 { 1337 as_bad (_("Illegal operand.")); 1338 return -1; 1339 } 1340 else if (oper->exp.X_op == O_absent) 1341 { 1342 as_bad (_("Missing operand.")); 1343 return -1; 1344 } 1345 1346 p = input_line_pointer; 1347 1348 if (mode == M6811_OP_NONE || mode == M6811_OP_DIRECT 1349 || mode == M6812_OP_D_IDX) 1350 { 1351 p = skip_whites (input_line_pointer); 1352 1353 if (*p == ',') 1354 { 1355 int possible_mode = M6811_OP_NONE; 1356 char *old_input_line; 1357 1358 old_input_line = p; 1359 p++; 1360 1361 /* 68HC12 pre increment or decrement. */ 1362 if (mode == M6811_OP_NONE) 1363 { 1364 if (*p == '-') 1365 { 1366 possible_mode = M6812_PRE_DEC; 1367 p++; 1368 } 1369 else if (*p == '+') 1370 { 1371 possible_mode = M6812_PRE_INC; 1372 p++; 1373 } 1374 p = skip_whites (p); 1375 } 1376 input_line_pointer = p; 1377 reg = register_name (); 1378 1379 /* Backtrack if we have a valid constant expression and 1380 it does not correspond to the offset of the 68HC12 indexed 1381 addressing mode (as in N,x). */ 1382 if (reg == REG_NONE && mode == M6811_OP_NONE 1383 && possible_mode != M6811_OP_NONE) 1384 { 1385 oper->mode = M6811_OP_IND16 | M6811_OP_JUMP_REL; 1386 input_line_pointer = skip_whites (old_input_line); 1387 return 1; 1388 } 1389 1390 if (possible_mode != M6811_OP_NONE) 1391 mode = possible_mode; 1392 1393 if ((current_architecture & cpu6811) 1394 && possible_mode != M6811_OP_NONE) 1395 as_bad (_("Pre-increment mode is not valid for 68HC11")); 1396 /* Backtrack. */ 1397 if (which == 0 && opmode & M6812_OP_IDX_P2 1398 && reg != REG_X && reg != REG_Y 1399 && reg != REG_PC && reg != REG_SP) 1400 { 1401 reg = REG_NONE; 1402 input_line_pointer = p; 1403 } 1404 1405 if (reg == REG_NONE && mode != M6811_OP_DIRECT 1406 && !(mode == M6811_OP_NONE && opmode & M6811_OP_IND16)) 1407 { 1408 as_bad (_("Wrong register in register indirect mode.")); 1409 return -1; 1410 } 1411 if (mode == M6812_OP_D_IDX) 1412 { 1413 p = skip_whites (input_line_pointer); 1414 if (*p++ != ']') 1415 { 1416 as_bad (_("Missing `]' to close register indirect operand.")); 1417 return -1; 1418 } 1419 input_line_pointer = p; 1420 oper->reg1 = reg; 1421 oper->mode = M6812_OP_D_IDX_2; 1422 return 1; 1423 } 1424 if (reg != REG_NONE) 1425 { 1426 oper->reg1 = reg; 1427 if (mode == M6811_OP_NONE) 1428 { 1429 p = input_line_pointer; 1430 if (*p == '-') 1431 { 1432 mode = M6812_POST_DEC; 1433 p++; 1434 if (current_architecture & cpu6811) 1435 as_bad 1436 (_("Post-decrement mode is not valid for 68HC11.")); 1437 } 1438 else if (*p == '+') 1439 { 1440 mode = M6812_POST_INC; 1441 p++; 1442 if (current_architecture & cpu6811) 1443 as_bad 1444 (_("Post-increment mode is not valid for 68HC11.")); 1445 } 1446 else 1447 mode = M6812_OP_IDX; 1448 1449 input_line_pointer = p; 1450 } 1451 else 1452 mode |= M6812_OP_IDX; 1453 1454 oper->mode = mode; 1455 return 1; 1456 } 1457 input_line_pointer = old_input_line; 1458 } 1459 1460 if (mode == M6812_OP_D_IDX_2) 1461 { 1462 as_bad (_("Invalid indexed indirect mode.")); 1463 return -1; 1464 } 1465 } 1466 1467 /* If the mode is not known until now, this is either a label 1468 or an indirect address. */ 1469 if (mode == M6811_OP_NONE) 1470 mode = M6811_OP_IND16 | M6811_OP_JUMP_REL; 1471 1472 p = input_line_pointer; 1473 while (*p == ' ' || *p == '\t') 1474 p++; 1475 input_line_pointer = p; 1476 oper->mode = mode; 1477 1478 return 1; 1479 } 1480 1481 #define M6812_AUTO_INC_DEC (M6812_PRE_INC | M6812_PRE_DEC \ 1482 | M6812_POST_INC | M6812_POST_DEC) 1483 1484 /* Checks that the number 'num' fits for a given mode. */ 1485 static int 1486 check_range (long num, int mode) 1487 { 1488 if (current_architecture == cpuxgate) 1489 { 1490 switch (mode) 1491 { 1492 case M68XG_OP_IMM3: 1493 return (num >= 0 && num <= 7) ? 1 : 0; 1494 1495 case M68XG_OP_R_IMM4: 1496 return (num >= 0 && num <= 15) ? 1 : 0; 1497 1498 case M68XG_OP_R_R_OFFS5: 1499 return (num >= 0 && num <= 31) ? 1 : 0; 1500 1501 case M68XG_OP_R_IMM8: 1502 return (num >= 0 && num <= 255) ? 1 : 0; 1503 1504 case M68XG_OP_R_IMM16: 1505 return (num >= 0 && num <= 65535) ? 1 : 0; 1506 1507 case M68XG_OP_B_MARKER: 1508 return (num >= -512 && num <= 511) ? 1 : 0; 1509 1510 case M68XG_OP_BRA_MARKER: 1511 return (num >= -1024 && num <= 1023) ? 1 : 0; 1512 1513 default: 1514 return 0; 1515 } 1516 } 1517 else 1518 { 1519 /* Auto increment and decrement are ok for [-8..8] without 0. */ 1520 if (mode & M6812_AUTO_INC_DEC) 1521 return (num != 0 && num <= 8 && num >= -8); 1522 1523 /* The 68HC12 supports 5, 9 and 16-bit offsets. */ 1524 if (mode & (M6812_INDEXED_IND | M6812_INDEXED | M6812_OP_IDX)) 1525 mode = M6811_OP_IND16; 1526 1527 if (mode & M6812_OP_JUMP_REL16) 1528 mode = M6811_OP_IND16; 1529 1530 mode &= ~M6811_OP_BRANCH; 1531 switch (mode) 1532 { 1533 case M6811_OP_IX: 1534 case M6811_OP_IY: 1535 case M6811_OP_DIRECT: 1536 return (num >= 0 && num <= 255) ? 1 : 0; 1537 1538 case M6811_OP_BITMASK: 1539 case M6811_OP_IMM8: 1540 case M6812_OP_PAGE: 1541 return (((num & 0xFFFFFF00) == 0) || ((num & 0xFFFFFF00) == 0xFFFFFF00)) 1542 ? 1 : 0; 1543 1544 case M6811_OP_JUMP_REL: 1545 return (num >= -128 && num <= 127) ? 1 : 0; 1546 1547 case M6811_OP_IND16: 1548 case M6811_OP_IND16 | M6812_OP_PAGE: 1549 case M6811_OP_IMM16: 1550 return (((num & 0xFFFF0000) == 0) || ((num & 0xFFFF0000) == 0xFFFF0000)) 1551 ? 1 : 0; 1552 1553 case M6812_OP_IBCC_MARKER: 1554 case M6812_OP_TBCC_MARKER: 1555 case M6812_OP_DBCC_MARKER: 1556 return (num >= -256 && num <= 255) ? 1 : 0; 1557 1558 case M6812_OP_TRAP_ID: 1559 return ((num >= 0x30 && num <= 0x39) 1560 || (num >= 0x40 && num <= 0x0ff)) ? 1 : 0; 1561 1562 default: 1563 return 0; 1564 } 1565 } 1566 } 1567 1568 /* Gas fixup generation. */ 1570 1571 /* Put a 1 byte expression described by 'oper'. If this expression contains 1572 unresolved symbols, generate an 8-bit fixup. */ 1573 static void 1574 fixup8 (expressionS *oper, int mode, int opmode) 1575 { 1576 char *f; 1577 1578 f = frag_more (1); 1579 1580 if (oper->X_op == O_constant) 1581 { 1582 if (mode & M6812_OP_TRAP_ID 1583 && !check_range (oper->X_add_number, M6812_OP_TRAP_ID)) 1584 { 1585 static char trap_id_warn_once = 0; 1586 1587 as_bad (_("Trap id `%ld' is out of range."), oper->X_add_number); 1588 if (trap_id_warn_once == 0) 1589 { 1590 trap_id_warn_once = 1; 1591 as_bad (_("Trap id must be within [0x30..0x39] or [0x40..0xff].")); 1592 } 1593 } 1594 1595 if (!(mode & M6812_OP_TRAP_ID) 1596 && !check_range (oper->X_add_number, mode)) 1597 { 1598 as_bad (_("Operand out of 8-bit range: `%ld'."), oper->X_add_number); 1599 } 1600 number_to_chars_bigendian (f, oper->X_add_number & 0x0FF, 1); 1601 } 1602 else if (oper->X_op != O_register) 1603 { 1604 if (mode & M6812_OP_TRAP_ID) 1605 as_bad (_("The trap id must be a constant.")); 1606 1607 if (mode == M6811_OP_JUMP_REL) 1608 { 1609 fix_new_exp (frag_now, f - frag_now->fr_literal, 1, 1610 oper, TRUE, BFD_RELOC_8_PCREL); 1611 } 1612 else 1613 { 1614 fixS *fixp; 1615 int reloc; 1616 1617 /* Now create an 8-bit fixup. If there was some %hi, %lo 1618 or %page modifier, generate the reloc accordingly. */ 1619 if (opmode & M6811_OP_HIGH_ADDR) 1620 reloc = BFD_RELOC_M68HC11_HI8; 1621 else if (opmode & M6811_OP_LOW_ADDR) 1622 reloc = BFD_RELOC_M68HC11_LO8; 1623 else if (opmode & M6811_OP_PAGE_ADDR) 1624 reloc = BFD_RELOC_M68HC11_PAGE; 1625 else 1626 reloc = BFD_RELOC_8; 1627 1628 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1, 1629 oper, FALSE, reloc); 1630 if (reloc != BFD_RELOC_8) 1631 fixp->fx_no_overflow = 1; 1632 } 1633 number_to_chars_bigendian (f, 0, 1); 1634 } 1635 else 1636 { 1637 as_fatal (_("Operand `%x' not recognized in fixup8."), oper->X_op); 1638 } 1639 } 1640 1641 /* Put a 2 byte expression described by 'oper'. If this expression contains 1642 unresolved symbols, generate a 16-bit fixup. */ 1643 static void 1644 fixup16 (expressionS *oper, int mode, int opmode ATTRIBUTE_UNUSED) 1645 { 1646 char *f; 1647 1648 f = frag_more (2); 1649 1650 if (oper->X_op == O_constant) 1651 { 1652 if (!check_range (oper->X_add_number, mode)) 1653 { 1654 as_bad (_("Operand out of 16-bit range: `%ld'."), 1655 oper->X_add_number); 1656 } 1657 number_to_chars_bigendian (f, oper->X_add_number & 0x0FFFF, 2); 1658 } 1659 else if (oper->X_op != O_register) 1660 { 1661 fixS *fixp; 1662 int reloc; 1663 1664 if ((opmode & M6811_OP_CALL_ADDR) && (mode & M6811_OP_IMM16)) 1665 reloc = BFD_RELOC_M68HC11_LO16; 1666 else if (mode & M6812_OP_JUMP_REL16) 1667 reloc = BFD_RELOC_16_PCREL; 1668 else if (mode & M6812_OP_PAGE) 1669 reloc = BFD_RELOC_M68HC11_LO16; 1670 else 1671 reloc = BFD_RELOC_16; 1672 1673 /* Now create a 16-bit fixup. */ 1674 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 2, 1675 oper, 1676 reloc == BFD_RELOC_16_PCREL, 1677 reloc); 1678 number_to_chars_bigendian (f, 0, 2); 1679 1680 if (reloc == BFD_RELOC_M68HC11_LO16) 1681 fixp->fx_no_overflow = 1; 1682 } 1683 else 1684 { 1685 as_fatal (_("Operand `%x' not recognized in fixup16."), oper->X_op); 1686 } 1687 } 1688 1689 /* Put a 3 byte expression described by 'oper'. If this expression contains 1690 unresolved symbols, generate a 24-bit fixup. */ 1691 static void 1692 fixup24 (expressionS *oper, int mode, int opmode ATTRIBUTE_UNUSED) 1693 { 1694 char *f; 1695 1696 f = frag_more (3); 1697 1698 if (oper->X_op == O_constant) 1699 { 1700 if (!check_range (oper->X_add_number, mode)) 1701 { 1702 as_bad (_("Operand out of 16-bit range: `%ld'."), 1703 oper->X_add_number); 1704 } 1705 number_to_chars_bigendian (f, oper->X_add_number & 0x0FFFFFF, 3); 1706 } 1707 else if (oper->X_op != O_register) 1708 { 1709 /* Now create a 24-bit fixup. */ 1710 fix_new_exp (frag_now, f - frag_now->fr_literal, 3, 1711 oper, FALSE, BFD_RELOC_M68HC11_24); 1712 number_to_chars_bigendian (f, 0, 3); 1713 } 1714 else 1715 { 1716 as_fatal (_("Operand `%x' not recognized in fixup16."), oper->X_op); 1717 } 1718 } 1719 1720 /* XGATE Put a 1 byte expression described by 'oper'. If this expression 1721 containts unresolved symbols, generate an 8-bit fixup. */ 1722 static void 1723 fixup8_xg (expressionS *oper, int mode, int opmode) 1724 { 1725 char *f; 1726 1727 f = frag_more (1); 1728 1729 if (oper->X_op == O_constant) 1730 { 1731 fixS *fixp; 1732 int reloc; 1733 1734 if ((opmode & M6811_OP_HIGH_ADDR) || (opmode & M6811_OP_LOW_ADDR)) 1735 { 1736 if (opmode & M6811_OP_HIGH_ADDR) 1737 reloc = BFD_RELOC_M68HC11_HI8; 1738 else 1739 reloc = BFD_RELOC_M68HC11_LO8; 1740 1741 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1, 1742 oper, FALSE, reloc); 1743 fixp->fx_no_overflow = 1; 1744 number_to_chars_bigendian (f, 0, 1); 1745 } 1746 else 1747 { 1748 if (!(check_range (oper->X_add_number, mode))) 1749 as_bad (_("Operand out of 8-bit range: `%ld'."), 1750 oper->X_add_number); 1751 number_to_chars_bigendian (f, oper->X_add_number & 0x0FF, 1); 1752 } 1753 } 1754 else if (oper->X_op != O_register) 1755 { 1756 if (mode == M68XG_OP_REL9) 1757 { 1758 /* Future improvement: 1759 This fixup/reloc isn't adding on constants to symbols. */ 1760 fix_new_exp (frag_now, f - frag_now->fr_literal -1, 2, 1761 oper, TRUE, BFD_RELOC_M68HC12_9_PCREL); 1762 } 1763 else if (mode == M68XG_OP_REL10) 1764 { 1765 /* Future improvement: 1766 This fixup/reloc isn't adding on constants to symbols. */ 1767 fix_new_exp (frag_now, f - frag_now->fr_literal -1, 2, 1768 oper, TRUE, BFD_RELOC_M68HC12_10_PCREL); 1769 } 1770 else 1771 { 1772 fixS *fixp; 1773 int reloc; 1774 1775 /* Now create an 8-bit fixup. If there was some %hi, %lo 1776 modifier, generate the reloc accordingly. */ 1777 if (opmode & M6811_OP_HIGH_ADDR) 1778 reloc = BFD_RELOC_M68HC11_HI8; 1779 else if (opmode & M6811_OP_LOW_ADDR) 1780 reloc = BFD_RELOC_M68HC11_LO8; 1781 else 1782 reloc = BFD_RELOC_8; 1783 1784 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1, 1785 oper, FALSE, reloc); 1786 if (reloc != BFD_RELOC_8) 1787 fixp->fx_no_overflow = 1; 1788 } 1789 number_to_chars_bigendian (f, 0, 1); 1790 } 1791 else 1792 as_fatal (_("Operand `%x' not recognized in fixup8."), oper->X_op); 1793 } 1794 1795 /* 68HC11 and 68HC12 code generation. */ 1797 1798 /* Translate the short branch/bsr instruction into a long branch. */ 1799 1800 static unsigned char 1801 convert_branch (unsigned char code) 1802 { 1803 if (IS_OPCODE (code, M6812_BSR)) 1804 return M6812_JSR; 1805 else if (IS_OPCODE (code, M6811_BSR)) 1806 return M6811_JSR; 1807 else if (IS_OPCODE (code, M6811_BRA)) 1808 return (current_architecture & cpu6812) ? M6812_JMP : M6811_JMP; 1809 else 1810 as_fatal (_("Unexpected branch conversion with `%x'"), code); 1811 1812 /* Keep gcc happy. */ 1813 return M6811_JSR; 1814 } 1815 1816 /* Start a new insn that contains at least 'size' bytes. Record the 1817 line information of that insn in the dwarf2 debug sections. */ 1818 static char * 1819 m68hc11_new_insn (int size) 1820 { 1821 char *f; 1822 1823 f = frag_more (size); 1824 1825 dwarf2_emit_insn (size); 1826 1827 return f; 1828 } 1829 1830 /* Builds a jump instruction (bra, bcc, bsr). */ 1831 static void 1832 build_jump_insn (struct m68hc11_opcode *opcode, operand operands[], 1833 int nb_operands, int jmp_mode) 1834 { 1835 unsigned char code; 1836 char *f; 1837 unsigned long n; 1838 1839 /* The relative branch conversion is not supported for 1840 brclr and brset. */ 1841 gas_assert ((opcode->format & M6811_OP_BITMASK) == 0); 1842 gas_assert (nb_operands == 1); 1843 gas_assert (operands[0].reg1 == REG_NONE && operands[0].reg2 == REG_NONE); 1844 1845 code = opcode->opcode; 1846 1847 n = operands[0].exp.X_add_number; 1848 1849 /* Turn into a long branch: 1850 - when force long branch option (and not for jbcc pseudos), 1851 - when jbcc and the constant is out of -128..127 range, 1852 - when branch optimization is allowed and branch out of range. */ 1853 if ((jmp_mode == 0 && flag_force_long_jumps) 1854 || (operands[0].exp.X_op == O_constant 1855 && (!check_range (n, opcode->format) && 1856 (jmp_mode == 1 || flag_fixed_branches == 0)))) 1857 { 1858 fix_new (frag_now, frag_now_fix (), 0, 1859 &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP); 1860 1861 if (code == M6811_BSR || code == M6811_BRA || code == M6812_BSR) 1862 { 1863 code = convert_branch (code); 1864 1865 f = m68hc11_new_insn (1); 1866 number_to_chars_bigendian (f, code, 1); 1867 } 1868 else if (current_architecture & cpu6812) 1869 { 1870 /* 68HC12: translate the bcc into a lbcc. */ 1871 f = m68hc11_new_insn (2); 1872 number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1); 1873 number_to_chars_bigendian (f + 1, code, 1); 1874 fixup16 (&operands[0].exp, M6812_OP_JUMP_REL16, 1875 M6812_OP_JUMP_REL16); 1876 return; 1877 } 1878 else 1879 { 1880 /* 68HC11: translate the bcc into b!cc +3; jmp <L>. */ 1881 f = m68hc11_new_insn (3); 1882 code ^= 1; 1883 number_to_chars_bigendian (f, code, 1); 1884 number_to_chars_bigendian (f + 1, 3, 1); 1885 number_to_chars_bigendian (f + 2, M6811_JMP, 1); 1886 } 1887 fixup16 (&operands[0].exp, M6811_OP_IND16, M6811_OP_IND16); 1888 return; 1889 } 1890 1891 /* Branch with a constant that must fit in 8-bits. */ 1892 if (operands[0].exp.X_op == O_constant) 1893 { 1894 if (!check_range (n, opcode->format)) 1895 { 1896 as_bad (_("Operand out of range for a relative branch: `%ld'"), 1897 n); 1898 } 1899 else if (opcode->format & M6812_OP_JUMP_REL16) 1900 { 1901 f = m68hc11_new_insn (4); 1902 number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1); 1903 number_to_chars_bigendian (f + 1, code, 1); 1904 number_to_chars_bigendian (f + 2, n & 0x0ffff, 2); 1905 } 1906 else 1907 { 1908 f = m68hc11_new_insn (2); 1909 number_to_chars_bigendian (f, code, 1); 1910 number_to_chars_bigendian (f + 1, n & 0x0FF, 1); 1911 } 1912 } 1913 else if (opcode->format & M6812_OP_JUMP_REL16) 1914 { 1915 fix_new (frag_now, frag_now_fix (), 0, 1916 &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP); 1917 1918 f = m68hc11_new_insn (2); 1919 number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1); 1920 number_to_chars_bigendian (f + 1, code, 1); 1921 fixup16 (&operands[0].exp, M6812_OP_JUMP_REL16, M6812_OP_JUMP_REL16); 1922 } 1923 else 1924 { 1925 char *op; 1926 1927 fix_new (frag_now, frag_now_fix (), 0, 1928 &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP); 1929 1930 /* Branch offset must fit in 8-bits, don't do some relax. */ 1931 if (jmp_mode == 0 && flag_fixed_branches) 1932 { 1933 op = m68hc11_new_insn (1); 1934 number_to_chars_bigendian (op, code, 1); 1935 fixup8 (&operands[0].exp, M6811_OP_JUMP_REL, M6811_OP_JUMP_REL); 1936 } 1937 1938 /* bra/bsr made be changed into jmp/jsr. */ 1939 else if (code == M6811_BSR || code == M6811_BRA || code == M6812_BSR) 1940 { 1941 /* Allocate worst case storage. */ 1942 op = m68hc11_new_insn (3); 1943 number_to_chars_bigendian (op, code, 1); 1944 number_to_chars_bigendian (op + 1, 0, 1); 1945 frag_variant (rs_machine_dependent, 1, 1, 1946 ENCODE_RELAX (STATE_PC_RELATIVE, STATE_UNDF), 1947 operands[0].exp.X_add_symbol, (offsetT) n, 1948 op); 1949 } 1950 else if (current_architecture & cpu6812) 1951 { 1952 op = m68hc11_new_insn (2); 1953 number_to_chars_bigendian (op, code, 1); 1954 number_to_chars_bigendian (op + 1, 0, 1); 1955 frag_var (rs_machine_dependent, 2, 2, 1956 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_UNDF), 1957 operands[0].exp.X_add_symbol, (offsetT) n, op); 1958 } 1959 else 1960 { 1961 op = m68hc11_new_insn (2); 1962 number_to_chars_bigendian (op, code, 1); 1963 number_to_chars_bigendian (op + 1, 0, 1); 1964 frag_var (rs_machine_dependent, 3, 3, 1965 ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_UNDF), 1966 operands[0].exp.X_add_symbol, (offsetT) n, op); 1967 } 1968 } 1969 } 1970 1971 /* Builds a dbne/dbeq/tbne/tbeq instruction. */ 1972 static void 1973 build_dbranch_insn (struct m68hc11_opcode *opcode, operand operands[], 1974 int nb_operands, int jmp_mode) 1975 { 1976 unsigned char code; 1977 char *f; 1978 unsigned long n; 1979 1980 /* The relative branch conversion is not supported for 1981 brclr and brset. */ 1982 gas_assert ((opcode->format & M6811_OP_BITMASK) == 0); 1983 gas_assert (nb_operands == 2); 1984 gas_assert (operands[0].reg1 != REG_NONE); 1985 1986 code = opcode->opcode & 0x0FF; 1987 1988 f = m68hc11_new_insn (1); 1989 number_to_chars_bigendian (f, code, 1); 1990 1991 n = operands[1].exp.X_add_number; 1992 code = operands[0].reg1; 1993 1994 if (operands[0].reg1 == REG_NONE || operands[0].reg1 == REG_CCR 1995 || operands[0].reg1 == REG_PC) 1996 as_bad (_("Invalid register for dbcc/tbcc instruction.")); 1997 1998 if (opcode->format & M6812_OP_IBCC_MARKER) 1999 code |= 0x80; 2000 else if (opcode->format & M6812_OP_TBCC_MARKER) 2001 code |= 0x40; 2002 2003 if (!(opcode->format & M6812_OP_EQ_MARKER)) 2004 code |= 0x20; 2005 2006 /* Turn into a long branch: 2007 - when force long branch option (and not for jbcc pseudos), 2008 - when jdbcc and the constant is out of -256..255 range, 2009 - when branch optimization is allowed and branch out of range. */ 2010 if ((jmp_mode == 0 && flag_force_long_jumps) 2011 || (operands[1].exp.X_op == O_constant 2012 && (!check_range (n, M6812_OP_IBCC_MARKER) && 2013 (jmp_mode == 1 || flag_fixed_branches == 0)))) 2014 { 2015 f = frag_more (2); 2016 code ^= 0x20; 2017 number_to_chars_bigendian (f, code, 1); 2018 number_to_chars_bigendian (f + 1, M6812_JMP, 1); 2019 fixup16 (&operands[0].exp, M6811_OP_IND16, M6811_OP_IND16); 2020 return; 2021 } 2022 2023 /* Branch with a constant that must fit in 9-bits. */ 2024 if (operands[1].exp.X_op == O_constant) 2025 { 2026 if (!check_range (n, M6812_OP_IBCC_MARKER)) 2027 { 2028 as_bad (_("Operand out of range for a relative branch: `%ld'"), 2029 n); 2030 } 2031 else 2032 { 2033 if ((long) n < 0) 2034 code |= 0x10; 2035 2036 f = frag_more (2); 2037 number_to_chars_bigendian (f, code, 1); 2038 number_to_chars_bigendian (f + 1, n & 0x0FF, 1); 2039 } 2040 } 2041 else 2042 { 2043 /* Branch offset must fit in 8-bits, don't do some relax. */ 2044 if (jmp_mode == 0 && flag_fixed_branches) 2045 { 2046 fixup8 (&operands[0].exp, M6811_OP_JUMP_REL, M6811_OP_JUMP_REL); 2047 } 2048 2049 else 2050 { 2051 f = frag_more (2); 2052 number_to_chars_bigendian (f, code, 1); 2053 number_to_chars_bigendian (f + 1, 0, 1); 2054 frag_var (rs_machine_dependent, 3, 3, 2055 ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_UNDF), 2056 operands[1].exp.X_add_symbol, (offsetT) n, f); 2057 } 2058 } 2059 } 2060 2061 #define OP_EXTENDED (M6811_OP_PAGE2 | M6811_OP_PAGE3 | M6811_OP_PAGE4) 2062 2063 /* Assemble the post index byte for 68HC12 extended addressing modes. */ 2064 2065 static int 2066 build_indexed_byte (operand *op, int format ATTRIBUTE_UNUSED, int move_insn) 2067 { 2068 unsigned char byte = 0; 2069 char *f; 2070 int mode; 2071 long val; 2072 2073 val = op->exp.X_add_number; 2074 mode = op->mode; 2075 if (mode & M6812_AUTO_INC_DEC) 2076 { 2077 byte = 0x20; 2078 if (mode & (M6812_POST_INC | M6812_POST_DEC)) 2079 byte |= 0x10; 2080 2081 if (op->exp.X_op == O_constant) 2082 { 2083 if (!check_range (val, mode)) 2084 as_bad (_("Increment/decrement value is out of range: `%ld'."), 2085 val); 2086 2087 if (mode & (M6812_POST_INC | M6812_PRE_INC)) 2088 byte |= (val - 1) & 0x07; 2089 else 2090 byte |= (8 - ((val) & 7)) | 0x8; 2091 } 2092 2093 switch (op->reg1) 2094 { 2095 case REG_NONE: 2096 as_fatal (_("Expecting a register.")); 2097 2098 case REG_X: 2099 byte |= 0; 2100 break; 2101 2102 case REG_Y: 2103 byte |= 0x40; 2104 break; 2105 2106 case REG_SP: 2107 byte |= 0x80; 2108 break; 2109 2110 default: 2111 as_bad (_("Invalid register for post/pre increment.")); 2112 break; 2113 } 2114 2115 f = frag_more (1); 2116 number_to_chars_bigendian (f, byte, 1); 2117 return 1; 2118 } 2119 2120 if (mode & (M6812_OP_IDX | M6812_OP_D_IDX_2)) 2121 { 2122 switch (op->reg1) 2123 { 2124 case REG_X: 2125 byte = 0; 2126 break; 2127 2128 case REG_Y: 2129 byte = 1; 2130 break; 2131 2132 case REG_SP: 2133 byte = 2; 2134 break; 2135 2136 case REG_PC: 2137 byte = 3; 2138 break; 2139 2140 default: 2141 as_bad (_("Invalid register.")); 2142 break; 2143 } 2144 2145 if (op->exp.X_op == O_constant) 2146 { 2147 if (!check_range (val, M6812_OP_IDX)) 2148 as_bad (_("Offset out of 16-bit range: %ld."), val); 2149 2150 if (move_insn && !(val >= -16 && val <= 15) 2151 && ((!(mode & M6812_OP_IDX) && !(mode & M6812_OP_D_IDX_2)) 2152 || !(current_architecture & cpu9s12x))) 2153 { 2154 as_bad (_("Offset out of 5-bit range for movw/movb insn: %ld."), 2155 val); 2156 return -1; 2157 } 2158 2159 if (val >= -16 && val <= 15 && !(mode & M6812_OP_D_IDX_2)) 2160 { 2161 byte = byte << 6; 2162 byte |= val & 0x1f; 2163 f = frag_more (1); 2164 number_to_chars_bigendian (f, byte, 1); 2165 return 1; 2166 } 2167 else if (val >= -256 && val <= 255 && !(mode & M6812_OP_D_IDX_2)) 2168 { 2169 byte = byte << 3; 2170 byte |= 0xe0; 2171 if (val < 0) 2172 byte |= 0x1; 2173 f = frag_more (2); 2174 number_to_chars_bigendian (f, byte, 1); 2175 number_to_chars_bigendian (f + 1, val & 0x0FF, 1); 2176 return 2; 2177 } 2178 else 2179 { 2180 byte = byte << 3; 2181 if (mode & M6812_OP_D_IDX_2) 2182 byte |= 0xe3; 2183 else 2184 byte |= 0xe2; 2185 2186 f = frag_more (3); 2187 number_to_chars_bigendian (f, byte, 1); 2188 number_to_chars_bigendian (f + 1, val & 0x0FFFF, 2); 2189 return 3; 2190 } 2191 } 2192 2193 if (mode & M6812_OP_D_IDX_2) 2194 { 2195 byte = (byte << 3) | 0xe3; 2196 f = frag_more (1); 2197 number_to_chars_bigendian (f, byte, 1); 2198 2199 fixup16 (&op->exp, 0, 0); 2200 } 2201 else if (op->reg1 != REG_PC) 2202 { 2203 symbolS *sym; 2204 offsetT off; 2205 2206 f = frag_more (1); 2207 number_to_chars_bigendian (f, byte, 1); 2208 sym = op->exp.X_add_symbol; 2209 off = op->exp.X_add_number; 2210 if (op->exp.X_op != O_symbol) 2211 { 2212 sym = make_expr_symbol (&op->exp); 2213 off = 0; 2214 } 2215 2216 /* movb/movw cannot be relaxed. */ 2217 if (move_insn) 2218 { 2219 if ((mode & M6812_OP_IDX) && (current_architecture & cpu9s12x)) 2220 { 2221 /* Must treat as a 16bit relocate as size of final result is unknown. */ 2222 2223 byte <<= 3; 2224 byte |= 0xe2; 2225 number_to_chars_bigendian (f, byte, 1); 2226 f = frag_more (2); 2227 fix_new (frag_now, f - frag_now->fr_literal, 2, 2228 sym, off, 0, BFD_RELOC_M68HC12_16B); 2229 return 1; 2230 } 2231 else 2232 { 2233 /* Non-S12X will fail at relocate stage if offset out of range. */ 2234 byte <<= 6; 2235 number_to_chars_bigendian (f, byte, 1); 2236 fix_new (frag_now, f - frag_now->fr_literal, 1, 2237 sym, off, 0, BFD_RELOC_M68HC12_5B); 2238 return 1; 2239 } 2240 } 2241 else 2242 { 2243 number_to_chars_bigendian (f, byte, 1); 2244 frag_var (rs_machine_dependent, 2, 2, 2245 ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_UNDF), 2246 sym, off, f); 2247 } 2248 } 2249 else 2250 { 2251 f = frag_more (1); 2252 2253 /* movb/movw cannot be relaxed. */ 2254 if (move_insn) 2255 { 2256 byte <<= 6; 2257 number_to_chars_bigendian (f, byte, 1); 2258 fix_new (frag_now, f - frag_now->fr_literal, 1, 2259 op->exp.X_add_symbol, op->exp.X_add_number, 0, BFD_RELOC_M68HC12_5B); 2260 return 1; 2261 } 2262 else 2263 { 2264 number_to_chars_bigendian (f, byte, 1); 2265 frag_var (rs_machine_dependent, 2, 2, 2266 ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_UNDF), 2267 op->exp.X_add_symbol, 2268 op->exp.X_add_number, f); 2269 } 2270 } 2271 return 3; 2272 } 2273 2274 if (mode & (M6812_OP_REG | M6812_OP_D_IDX)) 2275 { 2276 if (mode & M6812_OP_D_IDX) 2277 { 2278 if (op->reg1 != REG_D) 2279 as_bad (_("Expecting register D for indexed indirect mode.")); 2280 if ((move_insn) && (!(current_architecture & cpu9s12x))) 2281 as_bad (_("Indexed indirect mode is not allowed for movb/movw.")); 2282 2283 byte = 0xE7; 2284 } 2285 else 2286 { 2287 switch (op->reg1) 2288 { 2289 case REG_A: 2290 byte = 0xE4; 2291 break; 2292 2293 case REG_B: 2294 byte = 0xE5; 2295 break; 2296 2297 default: 2298 as_bad (_("Invalid accumulator register.")); 2299 2300 case REG_D: 2301 byte = 0xE6; 2302 break; 2303 } 2304 } 2305 switch (op->reg2) 2306 { 2307 case REG_X: 2308 break; 2309 2310 case REG_Y: 2311 byte |= (1 << 3); 2312 break; 2313 2314 case REG_SP: 2315 byte |= (2 << 3); 2316 break; 2317 2318 case REG_PC: 2319 byte |= (3 << 3); 2320 break; 2321 2322 default: 2323 as_bad (_("Invalid indexed register.")); 2324 break; 2325 } 2326 f = frag_more (1); 2327 number_to_chars_bigendian (f, byte, 1); 2328 return 1; 2329 } 2330 2331 fprintf (stderr, "mode = 0x%x\nop->reg1 = 0x%x\nop->reg2 = 0x%x\n", 2332 mode, op->reg1, op->reg2); 2333 as_fatal (_("Addressing mode not implemented yet.")); 2334 return 0; 2335 } 2336 2337 /* Assemble the 68HC12 register mode byte. */ 2338 static int 2339 build_reg_mode (operand *op, int format) 2340 { 2341 unsigned char byte; 2342 char *f; 2343 2344 if ((format & M6812_OP_SEX_MARKER) 2345 && (op->reg1 != REG_A) && (op->reg1 != REG_B) && (op->reg1 != REG_CCR) 2346 && (!(current_architecture & cpu9s12x))) 2347 as_bad (_("Invalid source register for this instruction, use 'tfr'.")); 2348 else if (op->reg1 == REG_NONE || op->reg1 == REG_PC) 2349 as_bad (_("Invalid source register.")); 2350 2351 if (format & M6812_OP_SEX_MARKER 2352 && op->reg2 != REG_D 2353 && op->reg2 != REG_X && op->reg2 != REG_Y && op->reg2 != REG_SP) 2354 as_bad (_("Invalid destination register for this instruction, use 'tfr'.")); 2355 else if (op->reg2 == REG_NONE || op->reg2 == REG_PC) 2356 as_bad (_("Invalid destination register.")); 2357 2358 byte = (op->reg1 << 4) | (op->reg2); 2359 if (format & M6812_OP_EXG_MARKER) 2360 byte |= 0x80; 2361 2362 if ((format & M6812_OP_SEX_MARKER) 2363 && (op->reg1 == REG_D) && (current_architecture & cpu9s12x)) 2364 byte |= 0x08; 2365 2366 f = frag_more (1); 2367 number_to_chars_bigendian (f, byte, 1); 2368 return 1; 2369 } 2370 2371 /* build_insn_xg takes a pointer to the opcode entry in the opcode table, 2372 the array of operand expressions and builds the corresponding instruction. */ 2373 2374 static void 2375 build_insn_xg (struct m68hc11_opcode *opcode, 2376 operand operands[], 2377 int nb_operands ATTRIBUTE_UNUSED) 2378 { 2379 char *f; 2380 long format; 2381 2382 /* Put the page code instruction if there is one. */ 2383 format = opcode->format; 2384 2385 if (!(operands[0].mode & (M6811_OP_LOW_ADDR | M6811_OP_HIGH_ADDR))) 2386 /* Need to retain those two modes, but clear for others. */ 2387 operands[0].mode = 0; 2388 2389 if (format & M68XG_OP_R_IMM8) 2390 { 2391 /* These opcodes are byte followed by imm8. */ 2392 f = m68hc11_new_insn (1); 2393 number_to_chars_bigendian (f, opcode->opcode >> 8, 1); 2394 fixup8_xg (&operands[0].exp, format, operands[0].mode); 2395 } 2396 else if (format & M68XG_OP_R_IMM16) 2397 { 2398 fixS *fixp; 2399 /* These opcodes expand into two imm8 instructions. 2400 Emit as low:high as per the Freescale datasheet. 2401 The linker requires them to be adjacent to handle the upper byte. */ 2402 2403 /* Build low byte. */ 2404 f = m68hc11_new_insn (1); 2405 number_to_chars_bigendian (f, opcode->opcode >> 8, 1); 2406 operands[0].mode = M6811_OP_LOW_ADDR; 2407 f = frag_more (1); 2408 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1, 2409 &operands[0].exp, FALSE, BFD_RELOC_M68HC12_LO8XG); 2410 fixp->fx_no_overflow = 1; 2411 number_to_chars_bigendian (f, 0, 1); 2412 2413 /* Build high byte. */ 2414 f = m68hc11_new_insn (1); 2415 number_to_chars_bigendian (f, (opcode->opcode >> 8) | 0x08, 1); 2416 operands[0].mode = M6811_OP_HIGH_ADDR; 2417 f = frag_more (1); 2418 fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1, 2419 &operands[0].exp, FALSE, BFD_RELOC_M68HC12_HI8XG); 2420 fixp->fx_no_overflow = 1; 2421 number_to_chars_bigendian (f, 0, 1); 2422 2423 } 2424 else if (format & M68XG_OP_REL9) 2425 { 2426 f = m68hc11_new_insn (1); 2427 number_to_chars_bigendian (f, opcode->opcode >> 8, 1); /* High byte. */ 2428 fixup8_xg (&operands[0].exp, format, M68XG_OP_REL9); 2429 } 2430 else if (format & M68XG_OP_REL10) 2431 { 2432 f = m68hc11_new_insn (1); 2433 number_to_chars_bigendian (f, opcode->opcode >> 8, 1); /* High byte. */ 2434 fixup8_xg (&operands[0].exp, format, M68XG_OP_REL10); 2435 } 2436 else 2437 { 2438 f = m68hc11_new_insn (2); 2439 number_to_chars_bigendian (f, opcode->opcode, 2); 2440 } 2441 return; 2442 } 2443 2444 /* build_insn takes a pointer to the opcode entry in the opcode table, 2445 the array of operand expressions and builds the corresponding instruction. 2446 This operation only deals with non relative jumps insn (need special 2447 handling). */ 2448 2449 static void 2450 build_insn (struct m68hc11_opcode *opcode, 2451 operand operands[], 2452 int nb_operands ATTRIBUTE_UNUSED) 2453 { 2454 int i; 2455 char *f; 2456 long format; 2457 int move_insn = 0; 2458 2459 /* Put the page code instruction if there is one. */ 2460 format = opcode->format; 2461 2462 if (format & M6811_OP_BRANCH) 2463 fix_new (frag_now, frag_now_fix (), 0, 2464 &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP); 2465 2466 if (format & OP_EXTENDED) 2467 { 2468 int page_code; 2469 2470 f = m68hc11_new_insn (2); 2471 if (format & M6811_OP_PAGE2) 2472 page_code = M6811_OPCODE_PAGE2; 2473 else if (format & M6811_OP_PAGE3) 2474 page_code = M6811_OPCODE_PAGE3; 2475 else 2476 page_code = M6811_OPCODE_PAGE4; 2477 2478 number_to_chars_bigendian (f, page_code, 1); 2479 f++; 2480 } 2481 else 2482 f = m68hc11_new_insn (1); 2483 2484 number_to_chars_bigendian (f, opcode->opcode, 1); 2485 2486 i = 0; 2487 2488 /* The 68HC12 movb and movw instructions are special. We have to handle 2489 them in a special way. */ 2490 if (format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2)) 2491 { 2492 move_insn = 1; 2493 if (format & M6812_OP_IDX) 2494 { 2495 build_indexed_byte (&operands[0], format, 1); 2496 i = 1; 2497 format &= ~M6812_OP_IDX; 2498 } 2499 if (format & M6812_OP_IDX_P2) 2500 { 2501 build_indexed_byte (&operands[1], format, 1); 2502 i = 0; 2503 format &= ~M6812_OP_IDX_P2; 2504 } 2505 } 2506 2507 if (format & (M6811_OP_DIRECT | M6811_OP_IMM8)) 2508 { 2509 fixup8 (&operands[i].exp, 2510 format & (M6811_OP_DIRECT | M6811_OP_IMM8 | M6812_OP_TRAP_ID), 2511 operands[i].mode); 2512 i++; 2513 } 2514 else if (IS_CALL_SYMBOL (format) && nb_operands == 1) 2515 { 2516 format &= ~M6812_OP_PAGE; 2517 fixup24 (&operands[i].exp, format & M6811_OP_IND16, 2518 operands[i].mode); 2519 i++; 2520 } 2521 else if (format & (M6811_OP_IMM16 | M6811_OP_IND16)) 2522 { 2523 fixup16 (&operands[i].exp, 2524 format & (M6811_OP_IMM16 | M6811_OP_IND16 | M6812_OP_PAGE), 2525 operands[i].mode); 2526 i++; 2527 } 2528 else if (format & (M6811_OP_IX | M6811_OP_IY)) 2529 { 2530 if ((format & M6811_OP_IX) && (operands[0].reg1 != REG_X)) 2531 as_bad (_("Invalid indexed register, expecting register X.")); 2532 if ((format & M6811_OP_IY) && (operands[0].reg1 != REG_Y)) 2533 as_bad (_("Invalid indexed register, expecting register Y.")); 2534 2535 fixup8 (&operands[0].exp, M6811_OP_IX, operands[0].mode); 2536 i = 1; 2537 } 2538 else if (format & 2539 (M6812_OP_IDX | M6812_OP_IDX_2 | M6812_OP_IDX_1 2540 | M6812_OP_D_IDX | M6812_OP_D_IDX_2)) 2541 { 2542 build_indexed_byte (&operands[i], format, move_insn); 2543 i++; 2544 } 2545 else if (format & M6812_OP_REG && current_architecture & cpu6812) 2546 { 2547 build_reg_mode (&operands[i], format); 2548 i++; 2549 } 2550 if (format & M6811_OP_BITMASK) 2551 { 2552 fixup8 (&operands[i].exp, M6811_OP_BITMASK, operands[i].mode); 2553 i++; 2554 } 2555 if (format & M6811_OP_JUMP_REL) 2556 { 2557 fixup8 (&operands[i].exp, M6811_OP_JUMP_REL, operands[i].mode); 2558 } 2559 else if (format & M6812_OP_IND16_P2) 2560 { 2561 fixup16 (&operands[1].exp, M6811_OP_IND16, operands[1].mode); 2562 } 2563 if (format & M6812_OP_PAGE) 2564 { 2565 fixup8 (&operands[i].exp, M6812_OP_PAGE, operands[i].mode); 2566 } 2567 } 2568 2569 /* Opcode identification and operand analysis. */ 2571 2572 /* find() gets a pointer to an entry in the opcode table. It must look at all 2573 opcodes with the same name and use the operands to choose the correct 2574 opcode. Returns the opcode pointer if there was a match and 0 if none. */ 2575 static struct m68hc11_opcode * 2576 find (struct m68hc11_opcode_def *opc, operand operands[], int nb_operands) 2577 { 2578 int i, match, pos; 2579 struct m68hc11_opcode *opcode; 2580 struct m68hc11_opcode *op_indirect; 2581 2582 op_indirect = 0; 2583 opcode = opc->opcode; 2584 2585 /* Now search the opcode table table for one with operands 2586 that matches what we've got. */ 2587 2588 if (current_architecture & cpuxgate) 2589 { 2590 /* Many XGATE insns are simple enough that we get an exact match. */ 2591 for (pos = match = 0; match == 0 && pos < opc->nb_modes; pos++, opcode++) 2592 if (opcode->format == operands[nb_operands-1].mode) 2593 return opcode; 2594 2595 return 0; 2596 } 2597 2598 /* Non XGATE */ 2599 2600 /* Now search the opcode table table for one with operands 2601 that matches what we've got. We're only done if the operands matched so 2602 far AND there are no more to check. */ 2603 for (pos = match = 0; match == 0 && pos < opc->nb_modes; pos++, opcode++) 2604 { 2605 int poss_indirect = 0; 2606 long format = opcode->format; 2607 int expect; 2608 2609 expect = 0; 2610 if (opcode->format & M6811_OP_MASK) 2611 expect++; 2612 if (opcode->format & M6811_OP_BITMASK) 2613 expect++; 2614 if (opcode->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) 2615 expect++; 2616 if (opcode->format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2)) 2617 expect++; 2618 if ((opcode->format & M6812_OP_PAGE) 2619 && (!IS_CALL_SYMBOL (opcode->format) || nb_operands == 2)) 2620 expect++; 2621 2622 for (i = 0; expect == nb_operands && i < nb_operands; i++) 2623 { 2624 int mode = operands[i].mode; 2625 2626 if (mode & M6811_OP_IMM16) 2627 { 2628 if (format & 2629 (M6811_OP_IMM8 | M6811_OP_IMM16 | M6811_OP_BITMASK)) 2630 continue; 2631 break; 2632 } 2633 if (mode == M6811_OP_DIRECT) 2634 { 2635 if (format & M6811_OP_DIRECT) 2636 continue; 2637 2638 /* If the operand is a page 0 operand, remember a 2639 possible <abs-16> addressing mode. We mark 2640 this and continue to check other operands. */ 2641 if (format & M6811_OP_IND16 2642 && flag_strict_direct_addressing && op_indirect == 0) 2643 { 2644 poss_indirect = 1; 2645 continue; 2646 } 2647 break; 2648 } 2649 if (mode & M6811_OP_IND16) 2650 { 2651 if (i == 0 && (format & M6811_OP_IND16) != 0) 2652 continue; 2653 if (i != 0 && (format & M6812_OP_PAGE) != 0) 2654 continue; 2655 if (i != 0 && (format & M6812_OP_IND16_P2) != 0) 2656 continue; 2657 if (i == 0 && (format & M6811_OP_BITMASK)) 2658 break; 2659 } 2660 if (mode & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) 2661 { 2662 if (format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) 2663 continue; 2664 } 2665 if (mode & M6812_OP_REG) 2666 { 2667 if (i == 0 2668 && (format & M6812_OP_REG) 2669 && (operands[i].reg2 == REG_NONE)) 2670 continue; 2671 if (i == 0 2672 && (format & M6812_OP_REG) 2673 && (format & M6812_OP_REG_2) 2674 && (operands[i].reg2 != REG_NONE)) 2675 continue; 2676 if (i == 0 2677 && (format & M6812_OP_IDX) 2678 && (operands[i].reg2 != REG_NONE)) 2679 continue; 2680 if (i == 0 2681 && (format & M6812_OP_IDX) 2682 && (format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2))) 2683 continue; 2684 if (i == 1 2685 && (format & M6812_OP_IDX_P2)) 2686 continue; 2687 break; 2688 } 2689 if (mode & M6812_OP_IDX) 2690 { 2691 if (format & M6811_OP_IX && operands[i].reg1 == REG_X) 2692 continue; 2693 if (format & M6811_OP_IY && operands[i].reg1 == REG_Y) 2694 continue; 2695 if (i == 0 2696 && format & (M6812_OP_IDX | M6812_OP_IDX_1 | M6812_OP_IDX_2) 2697 && (operands[i].reg1 == REG_X 2698 || operands[i].reg1 == REG_Y 2699 || operands[i].reg1 == REG_SP 2700 || operands[i].reg1 == REG_PC)) 2701 continue; 2702 if (i == 1 && (format & M6812_OP_IDX_P2)) 2703 continue; 2704 } 2705 if (mode & format & (M6812_OP_D_IDX | M6812_OP_D_IDX_2)) 2706 { 2707 if (i == 0) 2708 continue; 2709 } 2710 if (mode & M6812_AUTO_INC_DEC) 2711 { 2712 if (i == 0 2713 && format & (M6812_OP_IDX | M6812_OP_IDX_1 | 2714 M6812_OP_IDX_2)) 2715 continue; 2716 if (i == 1 && format & M6812_OP_IDX_P2) 2717 continue; 2718 } 2719 break; 2720 } 2721 match = i == nb_operands; 2722 2723 /* Operands are ok but an operand uses page 0 addressing mode 2724 while the insn supports abs-16 mode. Keep a reference to this 2725 insns in case there is no insn supporting page 0 addressing. */ 2726 if (match && poss_indirect) 2727 { 2728 op_indirect = opcode; 2729 match = 0; 2730 } 2731 if (match) 2732 break; 2733 } 2734 2735 /* Page 0 addressing is used but not supported by any insn. 2736 If absolute addresses are supported, we use that insn. */ 2737 if (match == 0 && op_indirect) 2738 { 2739 opcode = op_indirect; 2740 match = 1; 2741 } 2742 2743 return match ? opcode : 0; 2744 } 2745 2746 /* Find the real opcode and its associated operands. We use a progressive 2747 approach here. On entry, 'opc' points to the first opcode in the 2748 table that matches the opcode name in the source line. We try to 2749 isolate an operand, find a possible match in the opcode table. 2750 We isolate another operand if no match were found. The table 'operands' 2751 is filled while operands are recognized. 2752 2753 Returns the opcode pointer that matches the opcode name in the 2754 source line and the associated operands. */ 2755 static struct m68hc11_opcode * 2756 find_opcode (struct m68hc11_opcode_def *opc, operand operands[], 2757 int *nb_operands) 2758 { 2759 struct m68hc11_opcode *opcode; 2760 int i; 2761 2762 if (opc->max_operands == 0) 2763 { 2764 *nb_operands = 0; 2765 return opc->opcode; 2766 } 2767 2768 for (i = 0; i < opc->max_operands;) 2769 { 2770 int result; 2771 2772 result = get_operand (&operands[i], i, opc->format); 2773 if (result <= 0) 2774 return 0; 2775 2776 /* Special case where the bitmask of the bclr/brclr 2777 instructions is not introduced by #. 2778 Example: bclr 3,x $80. */ 2779 if (i == 1 && (opc->format & M6811_OP_BITMASK) 2780 && (operands[i].mode & M6811_OP_IND16)) 2781 { 2782 operands[i].mode = M6811_OP_IMM16; 2783 } 2784 2785 i += result; 2786 *nb_operands = i; 2787 if (i >= opc->min_operands) 2788 { 2789 opcode = find (opc, operands, i); 2790 2791 /* Another special case for 'call foo,page' instructions. 2792 Since we support 'call foo' and 'call foo,page' we must look 2793 if the optional page specification is present otherwise we will 2794 assemble immediately and treat the page spec as garbage. */ 2795 if (opcode && !(opcode->format & M6812_OP_PAGE)) 2796 return opcode; 2797 2798 if (opcode && *input_line_pointer != ',') 2799 return opcode; 2800 } 2801 2802 if (*input_line_pointer == ',') 2803 input_line_pointer++; 2804 } 2805 2806 return 0; 2807 } 2808 2809 #define M6812_XBCC_MARKER (M6812_OP_TBCC_MARKER \ 2810 | M6812_OP_DBCC_MARKER \ 2811 | M6812_OP_IBCC_MARKER) 2812 2813 /* Gas line assembler entry point. */ 2815 2816 /* This is the main entry point for the machine-dependent assembler. str 2817 points to a machine-dependent instruction. This function is supposed to 2818 emit the frags/bytes it assembles to. */ 2819 void 2820 md_assemble (char *str) 2821 { 2822 struct m68hc11_opcode_def *opc; 2823 struct m68hc11_opcode *opcode; 2824 2825 struct m68hc11_opcode opcode_local; 2826 unsigned char *op_start, *op_end; 2827 char *save; 2828 char name[20]; 2829 int nlen = 0; 2830 operand operands[M6811_MAX_OPERANDS]; 2831 int nb_operands = 0; 2832 int branch_optimize = 0; 2833 int alias_id = -1; 2834 2835 /* Drop leading whitespace. */ 2836 while (*str == ' ') 2837 str++; 2838 2839 /* Find the opcode end and get the opcode in 'name'. The opcode is forced 2840 lower case (the opcode table only has lower case op-codes). */ 2841 for (op_start = op_end = (unsigned char *) str; 2842 *op_end && !is_end_of_line[*op_end] && *op_end != ' '; 2843 op_end++) 2844 { 2845 name[nlen] = TOLOWER (op_start[nlen]); 2846 nlen++; 2847 if (nlen == sizeof (name) - 1) 2848 break; 2849 } 2850 name[nlen] = 0; 2851 2852 if (nlen == 0) 2853 { 2854 as_bad (_("No instruction or missing opcode.")); 2855 return; 2856 } 2857 2858 if (current_architecture == cpuxgate) 2859 { 2860 /* Find the opcode definition given its name. */ 2861 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name); 2862 if (opc == NULL) 2863 { 2864 as_bad (_("Opcode `%s' is not recognized."), name); 2865 return; 2866 } 2867 2868 /* Grab a local copy. */ 2869 opcode_local.name = opc->opcode->name; 2870 /* These will be incomplete where multiple variants exist. */ 2871 opcode_local.opcode = opc->opcode->opcode; 2872 opcode_local.format = opc->opcode->format; 2873 2874 save = input_line_pointer; 2875 input_line_pointer = (char *) op_end; 2876 2877 if (opc->format == M68XG_OP_NONE) 2878 { 2879 /* No special handling required. */ 2880 opcode_local.format = M68XG_OP_NONE; 2881 build_insn_xg (opc->opcode, operands, 0); 2882 return; 2883 } 2884 2885 /* Special handling of TFR. */ 2886 if (strncmp (opc->opcode->name, "tfr",3) == 0) 2887 { 2888 /* There must be two operands with a comma. */ 2889 input_line_pointer = skip_whites (input_line_pointer); 2890 operands[0].reg1 = register_name (); 2891 if (operands[0].reg1 == REG_NONE) 2892 { 2893 as_bad ("Invalid register\n"); 2894 return; 2895 } 2896 input_line_pointer = skip_whites (input_line_pointer); 2897 if (*input_line_pointer != ',') 2898 { 2899 as_bad ("Missing comma.\n"); 2900 return; 2901 } 2902 input_line_pointer++; 2903 input_line_pointer = skip_whites (input_line_pointer); 2904 operands[1].reg1 = register_name (); 2905 if (operands[1].reg1 == REG_NONE) 2906 { 2907 as_bad ("Invalid register\n"); 2908 return; 2909 } 2910 input_line_pointer = skip_whites (input_line_pointer); 2911 if (*input_line_pointer != '\n' && *input_line_pointer) 2912 { 2913 as_bad (_("Garbage at end of instruction: `%s'."), 2914 input_line_pointer); 2915 return; 2916 } 2917 if (operands[1].reg1 == REG_CCR) /* ,CCR */ 2918 opc->opcode->opcode = 0x00f8 | ( operands[0].reg1 << 8); 2919 else if (operands[0].reg1 == REG_CCR) /* CCR, */ 2920 opc->opcode->opcode = 0x00f9 | ( operands[1].reg1 << 8); 2921 else if (operands[1].reg1 == REG_PC) /* ,PC */ 2922 opc->opcode->opcode = 0x00fa | ( operands[0].reg1 << 8); 2923 else 2924 { 2925 as_bad ("Invalid operand to TFR\n"); 2926 return; 2927 } 2928 /* no special handling required */ 2929 opcode_local.format = M68XG_OP_NONE; 2930 opcode_local.opcode = opc->opcode->opcode; 2931 build_insn_xg (&opcode_local, operands, 0); 2932 return; 2933 } 2934 2935 /* CSEM, SSEM */ 2936 if (opc->format & M68XG_OP_IMM3) 2937 { 2938 /* Either IMM3 or R */ 2939 input_line_pointer = skip_whites (input_line_pointer); 2940 if ((*input_line_pointer == 'R') || (*input_line_pointer == 'r')) 2941 { 2942 operands[0].reg1 = register_name (); 2943 if (operands[0].reg1 == REG_NONE) 2944 { 2945 as_bad ("Invalid register\n"); 2946 return; 2947 } 2948 operands[0].mode = M68XG_OP_R; 2949 /* One opcode has multiple modes, so find right one. */ 2950 opcode = find (opc, operands, 1); 2951 if (opcode) 2952 { 2953 opcode_local.opcode = opcode->opcode 2954 | (operands[0].reg1 << 8); 2955 opcode_local.format = M68XG_OP_NONE; 2956 build_insn_xg (&opcode_local, operands, 1); 2957 } 2958 else 2959 as_bad ("No opcode found\n"); 2960 2961 return; 2962 } 2963 else 2964 { 2965 if (*input_line_pointer == '#') 2966 input_line_pointer++; 2967 2968 expression (&operands[0].exp); 2969 if (operands[0].exp.X_op == O_illegal) 2970 { 2971 as_bad (_("Illegal operand.")); 2972 return; 2973 } 2974 else if (operands[0].exp.X_op == O_absent) 2975 { 2976 as_bad (_("Missing operand.")); 2977 return; 2978 } 2979 2980 if (check_range (operands[0].exp.X_add_number,M68XG_OP_IMM3)) 2981 { 2982 opcode_local.opcode |= (operands[0].exp.X_add_number); 2983 operands[0].mode = M68XG_OP_IMM3; 2984 2985 opcode = find (opc, operands, 1); 2986 if (opcode) 2987 { 2988 opcode_local.opcode = opcode->opcode; 2989 opcode_local.opcode 2990 |= (operands[0].exp.X_add_number) << 8; 2991 opcode_local.format = M68XG_OP_NONE; 2992 build_insn_xg (&opcode_local, operands, 1); 2993 } 2994 else 2995 as_bad ("No opcode found\n"); 2996 2997 return; 2998 } 2999 else 3000 { 3001 as_bad ("Number out of range for IMM3\n"); 3002 return; 3003 } 3004 } 3005 } 3006 3007 /* Special handling of SIF. */ 3008 if (strncmp (opc->opcode->name, "sif",3) == 0) 3009 { 3010 /* Either OP_NONE or OP_RS. */ 3011 if (*input_line_pointer != '\n') 3012 input_line_pointer = skip_whites (input_line_pointer); 3013 3014 if ((*input_line_pointer == '\n') || (*input_line_pointer == '\r') 3015 || (*input_line_pointer == '\0')) 3016 opc->opcode->opcode = 0x0300; 3017 else 3018 { 3019 operands[0].reg1 = register_name (); 3020 if (operands[0].reg1 == REG_NONE) 3021 { 3022 as_bad ("Invalid register\n"); 3023 return; 3024 } 3025 opcode_local.opcode = 0x00f7 | (operands[0].reg1 << 8); 3026 } 3027 opcode_local.format = M68XG_OP_NONE; 3028 build_insn_xg (&opcode_local, operands, 0); 3029 return; 3030 } 3031 3032 /* SEX, PAR, JAL plus aliases NEG, TST, COM */ 3033 if (opc->format & M68XG_OP_R) 3034 { 3035 input_line_pointer = skip_whites (input_line_pointer); 3036 operands[0].reg1 = register_name (); 3037 if (operands[0].reg1 == REG_NONE) 3038 { 3039 as_bad ("Invalid register\n"); 3040 return; 3041 } 3042 if ((*input_line_pointer == '\n') || (*input_line_pointer == '\r') 3043 || (*input_line_pointer == '\0')) 3044 { 3045 /* Likely to be OP R. */ 3046 if (opc->format & M68XG_OP_R) 3047 { 3048 operands[0].mode = M68XG_OP_R; 3049 3050 opcode = find (opc, operands, 1); 3051 if (opcode) 3052 { 3053 if ((strncmp (opc->opcode->name, "com",3) == 0) 3054 || (strncmp (opc->opcode->name, "neg",3) == 0)) 3055 /* Special case for com RD as alias for sub RD,R0,RS */ 3056 /* Special case for neg RD as alias for sub RD,R0,RS */ 3057 opcode_local.opcode = opcode->opcode 3058 | (operands[0].reg1 << 8) | (operands[0].reg1 << 2); 3059 else if (strncmp (opc->opcode->name, "tst",3) == 0) 3060 /* Special case for tst RS alias for sub R0, RS, R0 */ 3061 opcode_local.opcode = opcode->opcode 3062 | (operands[0].reg1 << 5); 3063 else 3064 opcode_local.opcode |= (operands[0].reg1 << 8); 3065 } 3066 opcode_local.format = M68XG_OP_NONE; 3067 build_insn_xg (&opcode_local, operands, 0); 3068 } 3069 else 3070 as_bad ("No valid mode found\n"); 3071 3072 return; 3073 } 3074 } 3075 3076 if (opc->format & (M68XG_OP_REL9 | M68XG_OP_REL10)) 3077 { 3078 opcode_local.format = opc->format; 3079 input_line_pointer = skip_whites (input_line_pointer); 3080 expression (&operands[0].exp); 3081 if (operands[0].exp.X_op == O_illegal) 3082 { 3083 as_bad (_("Illegal operand.")); 3084 return; 3085 } 3086 else if (operands[0].exp.X_op == O_absent) 3087 { 3088 as_bad (_("Missing operand.")); 3089 return; 3090 } 3091 opcode_local.opcode = opc->opcode->opcode; 3092 build_insn_xg (&opcode_local, operands, 1); 3093 return; 3094 } 3095 3096 3097 /* For other command formats, parse input line and determine the mode 3098 we are using as we go. */ 3099 3100 input_line_pointer = skip_whites (input_line_pointer); 3101 if ((*input_line_pointer == '\n') || (*input_line_pointer == '\r') 3102 || (*input_line_pointer == '\0')) 3103 return; /* nothing left */ 3104 3105 if (*input_line_pointer == '#') 3106 { 3107 as_bad ("No register specified before hash\n"); 3108 return; 3109 } 3110 3111 /* first operand is expected to be a register */ 3112 if ((*input_line_pointer == 'R') || (*input_line_pointer == 'r')) 3113 { 3114 operands[0].reg1 = register_name (); 3115 if (operands[0].reg1 == REG_NONE) 3116 { 3117 as_bad ("Invalid register\n"); 3118 return; 3119 } 3120 } 3121 3122 input_line_pointer = skip_whites (input_line_pointer); 3123 if (*input_line_pointer != ',') 3124 { 3125 as_bad ("Missing operand\n"); 3126 return; 3127 } 3128 input_line_pointer++; 3129 input_line_pointer = skip_whites (input_line_pointer); 3130 3131 if (*input_line_pointer == '#') 3132 { 3133 /* Some kind of immediate mode, check if this is possible. */ 3134 if (!(opc->format 3135 & (M68XG_OP_R_IMM8 | M68XG_OP_R_IMM16 | M68XG_OP_R_IMM4))) 3136 as_bad ("Invalid immediate mode for `%s'", opc->opcode->name); 3137 else 3138 { 3139 input_line_pointer++; 3140 input_line_pointer = skip_whites (input_line_pointer); 3141 if (strncmp (input_line_pointer, "%hi", 3) == 0) 3142 { 3143 input_line_pointer += 3; 3144 operands[0].mode = M6811_OP_HIGH_ADDR; 3145 } 3146 else if (strncmp (input_line_pointer, "%lo", 3) == 0) 3147 { 3148 input_line_pointer += 3; 3149 operands[0].mode = M6811_OP_LOW_ADDR; 3150 } 3151 else 3152 operands[0].mode = 0; 3153 3154 expression (&operands[0].exp); 3155 if (operands[0].exp.X_op == O_illegal) 3156 { 3157 as_bad (_("Illegal operand.")); 3158 return; 3159 } 3160 else if (operands[0].exp.X_op == O_absent) 3161 { 3162 as_bad (_("Missing operand.")); 3163 return; 3164 } 3165 /* ok so far, can only be one mode */ 3166 opcode_local.format = opc->format 3167 & (M68XG_OP_R_IMM8 | M68XG_OP_R_IMM16 | M68XG_OP_R_IMM4); 3168 if (opcode_local.format & M68XG_OP_R_IMM4) 3169 { 3170 operands[0].mode = M68XG_OP_R_IMM4; 3171 /* same opcodes have multiple modes, so find right one */ 3172 opcode = find (opc, operands, 1); 3173 if (opcode) 3174 opcode_local.opcode = opcode->opcode 3175 | (operands[0].reg1 << 8); 3176 3177 if (operands[0].exp.X_op != O_constant) 3178 as_bad ("Only constants supported at for IMM4 mode\n"); 3179 else 3180 { 3181 if (check_range 3182 (operands[0].exp.X_add_number,M68XG_OP_R_IMM4)) 3183 opcode_local.opcode 3184 |= (operands[0].exp.X_add_number << 4); 3185 else 3186 as_bad ("Number out of range for IMM4\n"); 3187 } 3188 opcode_local.format = M68XG_OP_NONE; 3189 } 3190 else if (opcode_local.format & M68XG_OP_R_IMM16) 3191 { 3192 operands[0].mode = M68XG_OP_R_IMM16; 3193 3194 opcode = find (opc, operands, 1); 3195 if (opcode) 3196 { 3197 opcode_local.opcode = opcode->opcode 3198 | (operands[0].reg1 << 8); 3199 } 3200 } 3201 else 3202 { 3203 opcode_local.opcode = opc->opcode->opcode 3204 | (operands[0].reg1 << 8); 3205 } 3206 build_insn_xg (&opcode_local, operands, 1); 3207 } 3208 } 3209 else if ((*input_line_pointer == 'R') || (*input_line_pointer == 'r')) 3210 { 3211 /* we've got as far as OP R, R */ 3212 operands[1].reg1 = register_name (); 3213 if (operands[1].reg1 == REG_NONE) 3214 { 3215 as_bad ("Invalid register\n"); 3216 return; 3217 } 3218 if ((*input_line_pointer == '\n') || (*input_line_pointer == '\r') 3219 || (*input_line_pointer == '\0')) 3220 { 3221 /* looks like OP_R_R */ 3222 if (opc->format & M68XG_OP_R_R) 3223 { 3224 operands[0].mode = M68XG_OP_R_R; 3225 /* same opcodes have multiple modes, so find right one */ 3226 opcode = find (opc, operands, 1); 3227 if (opcode) 3228 { 3229 if ((strncmp (opc->opcode->name, "com",3) == 0) 3230 || (strncmp (opc->opcode->name, "mov",3) == 0) 3231 || (strncmp (opc->opcode->name, "neg",3) == 0)) 3232 { 3233 /* Special cases for: 3234 com RD, RS alias for xnor RD,R0,RS 3235 mov RD, RS alias for or RD, R0, RS 3236 neg RD, RS alias for sub RD, R0, RS */ 3237 opcode_local.opcode = opcode->opcode 3238 | (operands[0].reg1 << 8) | (operands[1].reg1 << 2); 3239 } 3240 else if ((strncmp (opc->opcode->name, "cmp",3) == 0) 3241 || (strncmp (opc->opcode->name, "cpc",3) == 0)) 3242 { 3243 /* special cases for: 3244 cmp RS1, RS2 alias for sub R0, RS1, RS2 3245 cpc RS1, RS2 alias for sbc R0, RS1, RS2 */ 3246 opcode_local.opcode = opcode->opcode 3247 | (operands[0].reg1 << 5) | (operands[1].reg1 << 2); 3248 } 3249 else 3250 { 3251 opcode_local.opcode = opcode->opcode 3252 | (operands[0].reg1 << 8) | (operands[1].reg1 << 5); 3253 } 3254 opcode_local.format = M68XG_OP_NONE; 3255 build_insn_xg (&opcode_local, operands, 1); 3256 } 3257 } 3258 else 3259 { 3260 as_bad ("No valid mode found\n"); 3261 } 3262 } 3263 else 3264 { 3265 /* more data */ 3266 if (*input_line_pointer != ',') 3267 { 3268 as_bad (_("Missing operand.")); 3269 return; 3270 } 3271 input_line_pointer++; 3272 input_line_pointer = skip_whites (input_line_pointer); 3273 if ((*input_line_pointer == 'R') || (*input_line_pointer == 'r')) 3274 { 3275 operands[2].reg1 = register_name (); 3276 if (operands[2].reg1 == REG_NONE) 3277 { 3278 as_bad ("Invalid register\n"); 3279 return; 3280 } 3281 if (opc->format & M68XG_OP_R_R_R) 3282 { 3283 operands[0].mode = M68XG_OP_R_R_R; 3284 3285 opcode = find (opc, operands, 1); 3286 if (opcode) 3287 { 3288 opcode_local.opcode = opcode->opcode 3289 | (operands[0].reg1 << 8) | (operands[1].reg1 << 5) 3290 | (operands[2].reg1 << 2); 3291 opcode_local.format = M68XG_OP_NONE; 3292 build_insn_xg (&opcode_local, operands, 1); 3293 } 3294 } 3295 else 3296 { 3297 as_bad ("No valid mode found\n"); 3298 } 3299 } 3300 } 3301 } 3302 else if (*input_line_pointer == '(') /* Indexed modes */ 3303 { 3304 input_line_pointer++; 3305 input_line_pointer = skip_whites (input_line_pointer); 3306 if ((*input_line_pointer == 'R') || (*input_line_pointer == 'r')) 3307 { 3308 /* we've got as far as OP R, (R */ 3309 operands[1].reg1 = register_name (); 3310 if (operands[1].reg1 == REG_NONE) 3311 { 3312 as_bad ("Invalid register\n"); 3313 return; 3314 } 3315 3316 if ((*input_line_pointer == '\n') || (*input_line_pointer == '\r') 3317 || (*input_line_pointer == '\0')) 3318 { 3319 /* Looks like OP_R_R. */ 3320 as_bad (_("Missing operand.")); 3321 return; 3322 } 3323 3324 input_line_pointer = skip_whites (input_line_pointer); 3325 3326 if (*input_line_pointer != ',') 3327 { 3328 as_bad (_("Missing operand.")); 3329 return; 3330 } 3331 input_line_pointer++; 3332 input_line_pointer = skip_whites (input_line_pointer); 3333 3334 if (*input_line_pointer == '#') 3335 { 3336 input_line_pointer++; 3337 input_line_pointer = skip_whites (input_line_pointer); 3338 expression (&operands[0].exp); 3339 if (operands[0].exp.X_op == O_illegal) 3340 { 3341 as_bad (_("Illegal operand.")); 3342 return; 3343 } 3344 else if (operands[0].exp.X_op == O_absent) 3345 { 3346 as_bad (_("Missing operand.")); 3347 return; 3348 } 3349 3350 input_line_pointer = skip_whites (input_line_pointer); 3351 if (*input_line_pointer != ')') 3352 { 3353 as_bad ("Missing `)' to close register indirect operand."); 3354 return; 3355 } 3356 else 3357 { 3358 input_line_pointer++; 3359 } 3360 3361 /* Ok so far, can only be one mode. */ 3362 opcode_local.format = M68XG_OP_R_R_OFFS5; 3363 operands[0].mode = M68XG_OP_R_R_OFFS5; 3364 3365 opcode = find (opc, operands, 1); 3366 if (opcode) 3367 { 3368 opcode_local.opcode = opcode->opcode 3369 | (operands[0].reg1 << 8) | (operands[1].reg1 << 5); 3370 if (operands[0].exp.X_op != O_constant) 3371 { 3372 as_bad 3373 ("Only constants supported for indexed OFFS5 mode\n"); 3374 } 3375 else 3376 { 3377 if (check_range (operands[0].exp.X_add_number, 3378 M68XG_OP_R_R_OFFS5)) 3379 { 3380 opcode_local.opcode 3381 |= (operands[0].exp.X_add_number); 3382 opcode_local.format = M68XG_OP_NONE; 3383 build_insn_xg (&opcode_local, operands, 1); 3384 } 3385 else 3386 { 3387 as_bad ("Number out of range for OFFS5\n"); 3388 } 3389 } 3390 } 3391 } 3392 else 3393 { 3394 operands[0].mode = M68XG_OP_RD_RB_RI; 3395 3396 if (*input_line_pointer == '-') 3397 { 3398 operands[0].mode = M68XG_OP_RD_RB_mRI; 3399 input_line_pointer++; 3400 } 3401 operands[2].reg1 = register_name (); 3402 if (operands[2].reg1 == REG_NONE) 3403 { 3404 as_bad ("Invalid register\n"); 3405 return; 3406 } 3407 3408 if (*input_line_pointer == '+') 3409 { 3410 if (opcode_local.format == M68XG_OP_RD_RB_mRI) 3411 { 3412 as_bad (_("Illegal operand.")); 3413 return; 3414 } 3415 operands[0].mode = M68XG_OP_RD_RB_RIp; 3416 input_line_pointer++; 3417 } 3418 3419 input_line_pointer = skip_whites (input_line_pointer); 3420 if (*input_line_pointer != ')') 3421 { 3422 as_bad 3423 ("Missing `)' to close register indirect operand."); 3424 return; 3425 } 3426 else 3427 { 3428 input_line_pointer++; 3429 } 3430 3431 opcode = find (opc, operands, 1); 3432 if (opcode) 3433 { 3434 opcode_local.opcode = opcode->opcode 3435 | (operands[0].reg1 << 8) | (operands[1].reg1 << 5) 3436 | (operands[2].reg1 << 2); 3437 opcode_local.format = M68XG_OP_NONE; 3438 build_insn_xg (&opcode_local, operands, 1); 3439 } 3440 else 3441 { 3442 as_bad ("Failed to find opcode for %s %s\n", 3443 opc->opcode->name, (char *)op_end); 3444 } 3445 } 3446 } 3447 } 3448 else 3449 { 3450 as_bad (_("Failed to find a valid mode for `%s'."), 3451 opc->opcode->name); 3452 } 3453 3454 if (opc->opcode && !flag_mri) 3455 { 3456 char *p = input_line_pointer; 3457 3458 while (*p == ' ' || *p == '\t' || *p == '\n' || *p == '\r') 3459 p++; 3460 3461 if (*p != '\n' && *p) 3462 as_bad (_("Garbage at end of instruction: `%s'."), p); 3463 } 3464 3465 input_line_pointer = save; 3466 3467 /* Opcode is known but does not have valid operands. Print out the 3468 syntax for this opcode. */ 3469 if (opc->opcode == 0) 3470 { 3471 if (flag_print_insn_syntax) 3472 print_insn_format (name); 3473 3474 as_bad (_("Invalid operand for `%s'"), name); 3475 return; 3476 } 3477 3478 return; 3479 } 3480 3481 /* Find the opcode definition given its name. */ 3482 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name); 3483 3484 /* If it's not recognized, look for 'jbsr' and 'jbxx'. These are 3485 pseudo insns for relative branch. For these branches, we always 3486 optimize them (turned into absolute branches) even if --short-branches 3487 is given. */ 3488 if (opc == NULL && name[0] == 'j' && name[1] == 'b') 3489 { 3490 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, &name[1]); 3491 if (opc 3492 && (!(opc->format & M6811_OP_JUMP_REL) 3493 || (opc->format & M6811_OP_BITMASK))) 3494 opc = 0; 3495 if (opc) 3496 branch_optimize = 1; 3497 } 3498 3499 /* The following test should probably be removed. This does not conform 3500 to Motorola assembler specs. */ 3501 if (opc == NULL && flag_mri) 3502 { 3503 if (*op_end == ' ' || *op_end == '\t') 3504 { 3505 while (*op_end == ' ' || *op_end == '\t') 3506 op_end++; 3507 3508 if (nlen < 19 3509 && (*op_end && 3510 (is_end_of_line[op_end[1]] 3511 || op_end[1] == ' ' || op_end[1] == '\t' 3512 || !ISALNUM (op_end[1]))) 3513 && (*op_end == 'a' || *op_end == 'b' 3514 || *op_end == 'A' || *op_end == 'B' 3515 || *op_end == 'd' || *op_end == 'D' 3516 || *op_end == 'x' || *op_end == 'X' 3517 || *op_end == 'y' || *op_end == 'Y')) 3518 { 3519 name[nlen++] = TOLOWER (*op_end++); 3520 name[nlen] = 0; 3521 opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, 3522 name); 3523 } 3524 } 3525 } 3526 3527 /* Identify a possible instruction alias. There are some on the 3528 68HC12 to emulate a few 68HC11 instructions. */ 3529 if (opc == NULL && (current_architecture & cpu6812)) 3530 { 3531 int i; 3532 3533 for (i = 0; i < m68hc12_num_alias; i++) 3534 if (strcmp (m68hc12_alias[i].name, name) == 0) 3535 { 3536 alias_id = i; 3537 break; 3538 } 3539 } 3540 if (opc == NULL && alias_id < 0) 3541 { 3542 as_bad (_("Opcode `%s' is not recognized."), name); 3543 return; 3544 } 3545 save = input_line_pointer; 3546 input_line_pointer = (char *) op_end; 3547 3548 if (opc) 3549 { 3550 opc->used++; 3551 opcode = find_opcode (opc, operands, &nb_operands); 3552 } 3553 else 3554 opcode = 0; 3555 3556 if ((opcode || alias_id >= 0) && !flag_mri) 3557 { 3558 char *p = input_line_pointer; 3559 3560 while (*p == ' ' || *p == '\t' || *p == '\n' || *p == '\r') 3561 p++; 3562 3563 if (*p != '\n' && *p) 3564 as_bad (_("Garbage at end of instruction: `%s'."), p); 3565 } 3566 3567 input_line_pointer = save; 3568 3569 if (alias_id >= 0) 3570 { 3571 char *f = m68hc11_new_insn (m68hc12_alias[alias_id].size); 3572 3573 number_to_chars_bigendian (f, m68hc12_alias[alias_id].code1, 1); 3574 if (m68hc12_alias[alias_id].size > 1) 3575 number_to_chars_bigendian (f + 1, m68hc12_alias[alias_id].code2, 1); 3576 3577 return; 3578 } 3579 3580 /* Opcode is known but does not have valid operands. Print out the 3581 syntax for this opcode. */ 3582 if (opcode == 0) 3583 { 3584 if (flag_print_insn_syntax) 3585 print_insn_format (name); 3586 3587 if (((strcmp (name, "movb") == 0) || (strcmp (name, "movw") == 0)) 3588 && (current_architecture & cpu9s12x)) 3589 { 3590 char *f; 3591 int movb; 3592 if (strcmp (name, "movb") == 0) 3593 movb = 8; 3594 else 3595 movb = 0; 3596 3597 /* The existing operand extract code fell over if these additional modes 3598 were enabled in m68hc11-opc.c. So they are commented there and 3599 decoded here instead. */ 3600 3601 if (operands[1].mode & (M6812_OP_IDX | M6812_OP_IDX_1 3602 | M6812_OP_IDX_2 | M6812_OP_D_IDX | M6812_OP_D_IDX_2 | M6812_PRE_INC 3603 | M6812_PRE_DEC | M6812_POST_INC | M6812_POST_DEC )) 3604 { 3605 /* first check if valid mode then start building it up */ 3606 if (operands[0].mode & (M6811_OP_IMM8 | M6811_OP_IMM16 3607 | M6811_OP_IND16 | M6812_OP_IDX | M6812_OP_IDX_1 3608 | M6812_OP_IDX_2 | M6812_OP_D_IDX | M6812_OP_D_IDX_2)) 3609 { 3610 int opr16a; 3611 if (operands[1].mode & (M6811_OP_IND16)) 3612 opr16a = 3; 3613 else 3614 opr16a = 0; 3615 3616 f = m68hc11_new_insn (2); 3617 3618 if (operands[0].mode & (M6811_OP_IMM8 | M6811_OP_IMM16)) 3619 { 3620 number_to_chars_bigendian (f, 0x1800 + movb + opr16a, 2); 3621 build_indexed_byte (&operands[1], operands[1].mode, 1); 3622 if (movb) 3623 fixup8 (&operands[0].exp, M6811_OP_IMM8, 3624 operands[0].mode); 3625 else 3626 fixup16 (&operands[0].exp, M6811_OP_IMM16, 3627 operands[0].mode); 3628 3629 return; 3630 } 3631 else if (operands[0].mode & M6811_OP_IND16) 3632 { 3633 number_to_chars_bigendian (f, 0x1801 + movb + opr16a, 2); 3634 build_indexed_byte (&operands[1], operands[1].mode, 1); 3635 fixup16 (&operands[0].exp, M6811_OP_IND16, operands[0].mode); 3636 return; 3637 } 3638 else 3639 { 3640 number_to_chars_bigendian (f, 0x1802 + movb + opr16a, 2); 3641 build_indexed_byte (&operands[0], operands[0].mode, 1); 3642 build_indexed_byte (&operands[1], operands[1].mode, 1); 3643 return; 3644 } 3645 } 3646 } 3647 else if (operands[1].mode & M6811_OP_IND16) 3648 { 3649 /* First check if this is valid mode, then start building it up. */ 3650 if (operands[0].mode & (M6811_OP_IMM8 | M6811_OP_IMM16 3651 | M6811_OP_IND16 | M6812_OP_IDX | M6812_OP_IDX_1 3652 | M6812_OP_IDX_2 | M6812_OP_D_IDX | M6812_OP_D_IDX_2)) 3653 { 3654 int opr16a; 3655 if (operands[1].mode & (M6811_OP_IND16)) 3656 opr16a = 3; 3657 else 3658 opr16a = 0; 3659 3660 f = m68hc11_new_insn (2); 3661 3662 /* The first two cases here should actually be covered by the 3663 normal operand code. */ 3664 if (operands[0].mode & (M6811_OP_IMM8 | M6811_OP_IMM16)) 3665 { 3666 number_to_chars_bigendian (f, 0x1800 + movb + opr16a, 2); 3667 if (movb) 3668 fixup8 (&operands[0].exp, M6811_OP_IMM8, operands[0].mode); 3669 else 3670 fixup16 (&operands[0].exp, M6811_OP_IMM16, operands[0].mode); 3671 3672 fixup16 (&operands[0].exp, M6811_OP_IND16, operands[0].mode); 3673 return; 3674 } 3675 else if (operands[0].mode & M6811_OP_IND16) 3676 { 3677 number_to_chars_bigendian (f, 0x1801 + movb + opr16a, 2); 3678 build_indexed_byte (&operands[1], operands[1].mode, 1); 3679 fixup16 (&operands[0].exp, M6811_OP_IND16, operands[0].mode); 3680 return; 3681 } 3682 else 3683 { 3684 number_to_chars_bigendian (f, 0x1802 + movb + opr16a, 2); 3685 build_indexed_byte (&operands[0], operands[0].mode, 1); 3686 fixup16 (&operands[1].exp, M6811_OP_IND16, operands[1].mode); 3687 return; 3688 } 3689 } 3690 } 3691 3692 as_bad (_("Invalid operand for `%s'"), name); 3693 return; 3694 3695 } 3696 else 3697 { 3698 as_bad (_("Invalid operand for `%s'"), name); 3699 return; 3700 } 3701 } 3702 3703 /* Treat dbeq/ibeq/tbeq instructions in a special way. The branch is 3704 relative and must be in the range -256..255 (9-bits). */ 3705 if ((opcode->format & M6812_XBCC_MARKER) 3706 && (opcode->format & M6811_OP_JUMP_REL)) 3707 build_dbranch_insn (opcode, operands, nb_operands, branch_optimize); 3708 3709 /* Relative jumps instructions are taken care of separately. We have to make 3710 sure that the relative branch is within the range -128..127. If it's out 3711 of range, the instructions are changed into absolute instructions. 3712 This is not supported for the brset and brclr instructions. */ 3713 else if ((opcode->format & (M6811_OP_JUMP_REL | M6812_OP_JUMP_REL16)) 3714 && !(opcode->format & M6811_OP_BITMASK)) 3715 build_jump_insn (opcode, operands, nb_operands, branch_optimize); 3716 else 3717 build_insn (opcode, operands, nb_operands); 3718 } 3719 3720 3721 /* Pseudo op to control the ELF flags. */ 3723 static void 3724 s_m68hc11_mode (int x ATTRIBUTE_UNUSED) 3725 { 3726 char *name = input_line_pointer, ch; 3727 3728 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 3729 input_line_pointer++; 3730 ch = *input_line_pointer; 3731 *input_line_pointer = '\0'; 3732 3733 if (strcmp (name, "mshort") == 0) 3734 { 3735 elf_flags &= ~E_M68HC11_I32; 3736 } 3737 else if (strcmp (name, "mlong") == 0) 3738 { 3739 elf_flags |= E_M68HC11_I32; 3740 } 3741 else if (strcmp (name, "mshort-double") == 0) 3742 { 3743 elf_flags &= ~E_M68HC11_F64; 3744 } 3745 else if (strcmp (name, "mlong-double") == 0) 3746 { 3747 elf_flags |= E_M68HC11_F64; 3748 } 3749 else 3750 { 3751 as_warn (_("Invalid mode: %s\n"), name); 3752 } 3753 *input_line_pointer = ch; 3754 demand_empty_rest_of_line (); 3755 } 3756 3757 /* Mark the symbols with STO_M68HC12_FAR to indicate the functions 3758 are using 'rtc' for returning. It is necessary to use 'call' 3759 to invoke them. This is also used by the debugger to correctly 3760 find the stack frame. */ 3761 static void 3762 s_m68hc11_mark_symbol (int mark) 3763 { 3764 char *name; 3765 int c; 3766 symbolS *symbolP; 3767 asymbol *bfdsym; 3768 elf_symbol_type *elfsym; 3769 3770 do 3771 { 3772 name = input_line_pointer; 3773 c = get_symbol_end (); 3774 symbolP = symbol_find_or_make (name); 3775 *input_line_pointer = c; 3776 3777 SKIP_WHITESPACE (); 3778 3779 bfdsym = symbol_get_bfdsym (symbolP); 3780 elfsym = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym); 3781 3782 gas_assert (elfsym); 3783 3784 /* Mark the symbol far (using rtc for function return). */ 3785 elfsym->internal_elf_sym.st_other |= mark; 3786 3787 if (c == ',') 3788 { 3789 input_line_pointer ++; 3790 3791 SKIP_WHITESPACE (); 3792 3793 if (*input_line_pointer == '\n') 3794 c = '\n'; 3795 } 3796 } 3797 while (c == ','); 3798 3799 demand_empty_rest_of_line (); 3800 } 3801 3802 static void 3803 s_m68hc11_relax (int ignore ATTRIBUTE_UNUSED) 3804 { 3805 expressionS ex; 3806 3807 expression (&ex); 3808 3809 if (ex.X_op != O_symbol || ex.X_add_number != 0) 3810 { 3811 as_bad (_("bad .relax format")); 3812 ignore_rest_of_line (); 3813 return; 3814 } 3815 3816 fix_new_exp (frag_now, frag_now_fix (), 0, &ex, 1, 3817 BFD_RELOC_M68HC11_RL_GROUP); 3818 3819 demand_empty_rest_of_line (); 3820 } 3821 3822 3823 /* Relocation, relaxation and frag conversions. */ 3825 3826 /* PC-relative offsets are relative to the start of the 3827 next instruction. That is, the address of the offset, plus its 3828 size, since the offset is always the last part of the insn. */ 3829 long 3830 md_pcrel_from (fixS *fixP) 3831 { 3832 if (fixP->fx_r_type == BFD_RELOC_M68HC11_RL_JUMP) 3833 return 0; 3834 3835 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; 3836 } 3837 3838 /* If while processing a fixup, a reloc really needs to be created 3839 then it is done here. */ 3840 arelent * 3841 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) 3842 { 3843 arelent *reloc; 3844 3845 reloc = (arelent *) xmalloc (sizeof (arelent)); 3846 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3847 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 3848 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3849 if (fixp->fx_r_type == 0) 3850 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16); 3851 else 3852 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); 3853 if (reloc->howto == (reloc_howto_type *) NULL) 3854 { 3855 as_bad_where (fixp->fx_file, fixp->fx_line, 3856 _("Relocation %d is not supported by object file format."), 3857 (int) fixp->fx_r_type); 3858 return NULL; 3859 } 3860 3861 /* Since we use Rel instead of Rela, encode the vtable entry to be 3862 used in the relocation's section offset. */ 3863 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3864 reloc->address = fixp->fx_offset; 3865 3866 reloc->addend = 0; 3867 return reloc; 3868 } 3869 3870 /* We need a port-specific relaxation function to cope with sym2 - sym1 3871 relative expressions with both symbols in the same segment (but not 3872 necessarily in the same frag as this insn), for example: 3873 ldab sym2-(sym1-2),pc 3874 sym1: 3875 The offset can be 5, 9 or 16 bits long. */ 3876 3877 long 3878 m68hc11_relax_frag (segT seg ATTRIBUTE_UNUSED, fragS *fragP, 3879 long stretch ATTRIBUTE_UNUSED) 3880 { 3881 long growth; 3882 offsetT aim = 0; 3883 symbolS *symbolP; 3884 const relax_typeS *this_type; 3885 const relax_typeS *start_type; 3886 relax_substateT next_state; 3887 relax_substateT this_state; 3888 const relax_typeS *table = TC_GENERIC_RELAX_TABLE; 3889 3890 /* We only have to cope with frags as prepared by 3891 md_estimate_size_before_relax. The STATE_BITS16 case may geet here 3892 because of the different reasons that it's not relaxable. */ 3893 switch (fragP->fr_subtype) 3894 { 3895 case ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_BITS16): 3896 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS16): 3897 /* When we get to this state, the frag won't grow any more. */ 3898 return 0; 3899 3900 case ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_BITS5): 3901 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS5): 3902 case ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_BITS9): 3903 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS9): 3904 if (fragP->fr_symbol == NULL 3905 || S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) 3906 as_fatal (_("internal inconsistency problem in %s: fr_symbol %lx"), 3907 __FUNCTION__, (long) fragP->fr_symbol); 3908 symbolP = fragP->fr_symbol; 3909 if (symbol_resolved_p (symbolP)) 3910 as_fatal (_("internal inconsistency problem in %s: resolved symbol"), 3911 __FUNCTION__); 3912 aim = S_GET_VALUE (symbolP); 3913 break; 3914 3915 default: 3916 as_fatal (_("internal inconsistency problem in %s: fr_subtype %d"), 3917 __FUNCTION__, fragP->fr_subtype); 3918 } 3919 3920 /* The rest is stolen from relax_frag. There's no obvious way to 3921 share the code, but fortunately no requirement to keep in sync as 3922 long as fragP->fr_symbol does not have its segment changed. */ 3923 3924 this_state = fragP->fr_subtype; 3925 start_type = this_type = table + this_state; 3926 3927 if (aim < 0) 3928 { 3929 /* Look backwards. */ 3930 for (next_state = this_type->rlx_more; next_state;) 3931 if (aim >= this_type->rlx_backward) 3932 next_state = 0; 3933 else 3934 { 3935 /* Grow to next state. */ 3936 this_state = next_state; 3937 this_type = table + this_state; 3938 next_state = this_type->rlx_more; 3939 } 3940 } 3941 else 3942 { 3943 /* Look forwards. */ 3944 for (next_state = this_type->rlx_more; next_state;) 3945 if (aim <= this_type->rlx_forward) 3946 next_state = 0; 3947 else 3948 { 3949 /* Grow to next state. */ 3950 this_state = next_state; 3951 this_type = table + this_state; 3952 next_state = this_type->rlx_more; 3953 } 3954 } 3955 3956 growth = this_type->rlx_length - start_type->rlx_length; 3957 if (growth != 0) 3958 fragP->fr_subtype = this_state; 3959 return growth; 3960 } 3961 3962 void 3963 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, asection *sec ATTRIBUTE_UNUSED, 3964 fragS *fragP) 3965 { 3966 long value; 3967 long disp; 3968 char *buffer_address = fragP->fr_literal; 3969 3970 /* Address in object code of the displacement. */ 3971 int object_address = fragP->fr_fix + fragP->fr_address; 3972 3973 buffer_address += fragP->fr_fix; 3974 3975 /* The displacement of the address, from current location. */ 3976 value = S_GET_VALUE (fragP->fr_symbol); 3977 disp = (value + fragP->fr_offset) - object_address; 3978 3979 switch (fragP->fr_subtype) 3980 { 3981 case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_BYTE): 3982 fragP->fr_opcode[1] = disp; 3983 break; 3984 3985 case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_WORD): 3986 /* This relax is only for bsr and bra. */ 3987 gas_assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR) 3988 || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA) 3989 || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR)); 3990 3991 fragP->fr_opcode[0] = convert_branch (fragP->fr_opcode[0]); 3992 3993 fix_new (fragP, fragP->fr_fix - 1, 2, 3994 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16); 3995 fragP->fr_fix += 1; 3996 break; 3997 3998 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_BYTE): 3999 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_BYTE): 4000 fragP->fr_opcode[1] = disp; 4001 break; 4002 4003 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_WORD): 4004 /* Invert branch. */ 4005 fragP->fr_opcode[0] ^= 1; 4006 fragP->fr_opcode[1] = 3; /* Branch offset. */ 4007 buffer_address[0] = M6811_JMP; 4008 fix_new (fragP, fragP->fr_fix + 1, 2, 4009 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16); 4010 fragP->fr_fix += 3; 4011 break; 4012 4013 case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_WORD): 4014 /* Translate branch into a long branch. */ 4015 fragP->fr_opcode[1] = fragP->fr_opcode[0]; 4016 fragP->fr_opcode[0] = M6811_OPCODE_PAGE2; 4017 4018 fix_new (fragP, fragP->fr_fix, 2, 4019 fragP->fr_symbol, fragP->fr_offset, 1, 4020 BFD_RELOC_16_PCREL); 4021 fragP->fr_fix += 2; 4022 break; 4023 4024 case ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_BITS5): 4025 if (fragP->fr_symbol != 0 4026 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) 4027 value = disp; 4028 /* fall through */ 4029 4030 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS5): 4031 fragP->fr_opcode[0] = fragP->fr_opcode[0] << 6; 4032 fragP->fr_opcode[0] |= value & 0x1f; 4033 break; 4034 4035 case ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_BITS9): 4036 /* For a PC-relative offset, use the displacement with a -1 correction 4037 to take into account the additional byte of the insn. */ 4038 if (fragP->fr_symbol != 0 4039 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) 4040 value = disp - 1; 4041 /* fall through */ 4042 4043 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS9): 4044 fragP->fr_opcode[0] = (fragP->fr_opcode[0] << 3); 4045 fragP->fr_opcode[0] |= 0xE0; 4046 fragP->fr_opcode[0] |= (value >> 8) & 1; 4047 fragP->fr_opcode[1] = value; 4048 fragP->fr_fix += 1; 4049 break; 4050 4051 case ENCODE_RELAX (STATE_INDEXED_PCREL, STATE_BITS16): 4052 case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS16): 4053 fragP->fr_opcode[0] = (fragP->fr_opcode[0] << 3); 4054 fragP->fr_opcode[0] |= 0xe2; 4055 if ((fragP->fr_opcode[0] & 0x0ff) == 0x0fa 4056 && fragP->fr_symbol != 0 4057 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) 4058 { 4059 fix_new (fragP, fragP->fr_fix, 2, 4060 fragP->fr_symbol, fragP->fr_offset, 4061 1, BFD_RELOC_16_PCREL); 4062 } 4063 else 4064 { 4065 fix_new (fragP, fragP->fr_fix, 2, 4066 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16); 4067 } 4068 fragP->fr_fix += 2; 4069 break; 4070 4071 case ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_BYTE): 4072 if (disp < 0) 4073 fragP->fr_opcode[0] |= 0x10; 4074 4075 fragP->fr_opcode[1] = disp & 0x0FF; 4076 break; 4077 4078 case ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_WORD): 4079 /* Invert branch. */ 4080 fragP->fr_opcode[0] ^= 0x20; 4081 fragP->fr_opcode[1] = 3; /* Branch offset. */ 4082 buffer_address[0] = M6812_JMP; 4083 fix_new (fragP, fragP->fr_fix + 1, 2, 4084 fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16); 4085 fragP->fr_fix += 3; 4086 break; 4087 4088 default: 4089 break; 4090 } 4091 } 4092 4093 /* On an ELF system, we can't relax a weak symbol. The weak symbol 4094 can be overridden at final link time by a non weak symbol. We can 4095 relax externally visible symbol because there is no shared library 4096 and such symbol can't be overridden (unless they are weak). */ 4097 static int 4098 relaxable_symbol (symbolS *symbol) 4099 { 4100 return ! S_IS_WEAK (symbol); 4101 } 4102 4103 /* Force truly undefined symbols to their maximum size, and generally set up 4104 the frag list to be relaxed. */ 4105 int 4106 md_estimate_size_before_relax (fragS *fragP, asection *segment) 4107 { 4108 if (RELAX_LENGTH (fragP->fr_subtype) == STATE_UNDF) 4109 { 4110 if (S_GET_SEGMENT (fragP->fr_symbol) != segment 4111 || !relaxable_symbol (fragP->fr_symbol) 4112 || (segment != absolute_section 4113 && RELAX_STATE (fragP->fr_subtype) == STATE_INDEXED_OFFSET)) 4114 { 4115 /* Non-relaxable cases. */ 4116 int old_fr_fix; 4117 char *buffer_address; 4118 4119 old_fr_fix = fragP->fr_fix; 4120 buffer_address = fragP->fr_fix + fragP->fr_literal; 4121 4122 switch (RELAX_STATE (fragP->fr_subtype)) 4123 { 4124 case STATE_PC_RELATIVE: 4125 4126 /* This relax is only for bsr and bra. */ 4127 gas_assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR) 4128 || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA) 4129 || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR)); 4130 4131 if (flag_fixed_branches) 4132 as_bad_where (fragP->fr_file, fragP->fr_line, 4133 _("bra or bsr with undefined symbol.")); 4134 4135 /* The symbol is undefined or in a separate section. 4136 Turn bra into a jmp and bsr into a jsr. The insn 4137 becomes 3 bytes long (instead of 2). A fixup is 4138 necessary for the unresolved symbol address. */ 4139 fragP->fr_opcode[0] = convert_branch (fragP->fr_opcode[0]); 4140 4141 fix_new (fragP, fragP->fr_fix - 1, 2, fragP->fr_symbol, 4142 fragP->fr_offset, 0, BFD_RELOC_16); 4143 fragP->fr_fix++; 4144 break; 4145 4146 case STATE_CONDITIONAL_BRANCH: 4147 gas_assert (current_architecture & cpu6811); 4148 4149 fragP->fr_opcode[0] ^= 1; /* Reverse sense of branch. */ 4150 fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */ 4151 4152 /* Don't use fr_opcode[2] because this may be 4153 in a different frag. */ 4154 buffer_address[0] = M6811_JMP; 4155 4156 fragP->fr_fix++; 4157 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 4158 fragP->fr_offset, 0, BFD_RELOC_16); 4159 fragP->fr_fix += 2; 4160 break; 4161 4162 case STATE_INDEXED_OFFSET: 4163 gas_assert (current_architecture & cpu6812); 4164 4165 if (fragP->fr_symbol 4166 && S_GET_SEGMENT (fragP->fr_symbol) == absolute_section) 4167 { 4168 fragP->fr_subtype = ENCODE_RELAX (STATE_INDEXED_OFFSET, 4169 STATE_BITS5); 4170 /* Return the size of the variable part of the frag. */ 4171 return md_relax_table[fragP->fr_subtype].rlx_length; 4172 } 4173 else 4174 { 4175 /* Switch the indexed operation to 16-bit mode. */ 4176 fragP->fr_opcode[0] = fragP->fr_opcode[0] << 3; 4177 fragP->fr_opcode[0] |= 0xe2; 4178 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 4179 fragP->fr_offset, 0, BFD_RELOC_16); 4180 fragP->fr_fix += 2; 4181 } 4182 break; 4183 4184 case STATE_INDEXED_PCREL: 4185 gas_assert (current_architecture & cpu6812); 4186 4187 if (fragP->fr_symbol 4188 && S_GET_SEGMENT (fragP->fr_symbol) == absolute_section) 4189 { 4190 fragP->fr_subtype = ENCODE_RELAX (STATE_INDEXED_PCREL, 4191 STATE_BITS5); 4192 /* Return the size of the variable part of the frag. */ 4193 return md_relax_table[fragP->fr_subtype].rlx_length; 4194 } 4195 else 4196 { 4197 fragP->fr_opcode[0] = fragP->fr_opcode[0] << 3; 4198 fragP->fr_opcode[0] |= 0xe2; 4199 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 4200 fragP->fr_offset, 1, BFD_RELOC_16_PCREL); 4201 fragP->fr_fix += 2; 4202 } 4203 break; 4204 4205 case STATE_XBCC_BRANCH: 4206 gas_assert (current_architecture & cpu6812); 4207 4208 fragP->fr_opcode[0] ^= 0x20; /* Reverse sense of branch. */ 4209 fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */ 4210 4211 /* Don't use fr_opcode[2] because this may be 4212 in a different frag. */ 4213 buffer_address[0] = M6812_JMP; 4214 4215 fragP->fr_fix++; 4216 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 4217 fragP->fr_offset, 0, BFD_RELOC_16); 4218 fragP->fr_fix += 2; 4219 break; 4220 4221 case STATE_CONDITIONAL_BRANCH_6812: 4222 gas_assert (current_architecture & cpu6812); 4223 4224 /* Translate into a lbcc branch. */ 4225 fragP->fr_opcode[1] = fragP->fr_opcode[0]; 4226 fragP->fr_opcode[0] = M6811_OPCODE_PAGE2; 4227 4228 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, 4229 fragP->fr_offset, 1, BFD_RELOC_16_PCREL); 4230 fragP->fr_fix += 2; 4231 break; 4232 4233 default: 4234 as_fatal (_("Subtype %d is not recognized."), fragP->fr_subtype); 4235 } 4236 frag_wane (fragP); 4237 4238 /* Return the growth in the fixed part of the frag. */ 4239 return fragP->fr_fix - old_fr_fix; 4240 } 4241 4242 /* Relaxable cases. */ 4243 switch (RELAX_STATE (fragP->fr_subtype)) 4244 { 4245 case STATE_PC_RELATIVE: 4246 /* This relax is only for bsr and bra. */ 4247 gas_assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR) 4248 || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA) 4249 || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR)); 4250 4251 fragP->fr_subtype = ENCODE_RELAX (STATE_PC_RELATIVE, STATE_BYTE); 4252 break; 4253 4254 case STATE_CONDITIONAL_BRANCH: 4255 gas_assert (current_architecture & cpu6811); 4256 4257 fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, 4258 STATE_BYTE); 4259 break; 4260 4261 case STATE_INDEXED_OFFSET: 4262 gas_assert (current_architecture & cpu6812); 4263 4264 fragP->fr_subtype = ENCODE_RELAX (STATE_INDEXED_OFFSET, 4265 STATE_BITS5); 4266 break; 4267 4268 case STATE_INDEXED_PCREL: 4269 gas_assert (current_architecture & cpu6812); 4270 4271 fragP->fr_subtype = ENCODE_RELAX (STATE_INDEXED_PCREL, 4272 STATE_BITS5); 4273 break; 4274 4275 case STATE_XBCC_BRANCH: 4276 gas_assert (current_architecture & cpu6812); 4277 4278 fragP->fr_subtype = ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_BYTE); 4279 break; 4280 4281 case STATE_CONDITIONAL_BRANCH_6812: 4282 gas_assert (current_architecture & cpu6812); 4283 4284 fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, 4285 STATE_BYTE); 4286 break; 4287 } 4288 } 4289 4290 if (fragP->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0])) 4291 as_fatal (_("Subtype %d is not recognized."), fragP->fr_subtype); 4292 4293 /* Return the size of the variable part of the frag. */ 4294 return md_relax_table[fragP->fr_subtype].rlx_length; 4295 } 4296 4297 /* See whether we need to force a relocation into the output file. */ 4298 int 4299 tc_m68hc11_force_relocation (fixS *fixP) 4300 { 4301 if (fixP->fx_r_type == BFD_RELOC_M68HC11_RL_GROUP) 4302 return 1; 4303 4304 return generic_force_reloc (fixP); 4305 } 4306 4307 /* Here we decide which fixups can be adjusted to make them relative 4308 to the beginning of the section instead of the symbol. Basically 4309 we need to make sure that the linker relaxation is done 4310 correctly, so in some cases we force the original symbol to be 4311 used. */ 4312 int 4313 tc_m68hc11_fix_adjustable (fixS *fixP) 4314 { 4315 switch (fixP->fx_r_type) 4316 { 4317 /* For the linker relaxation to work correctly, these relocs 4318 need to be on the symbol itself. */ 4319 case BFD_RELOC_16: 4320 case BFD_RELOC_M68HC11_RL_JUMP: 4321 case BFD_RELOC_M68HC11_RL_GROUP: 4322 case BFD_RELOC_VTABLE_INHERIT: 4323 case BFD_RELOC_VTABLE_ENTRY: 4324 case BFD_RELOC_32: 4325 4326 /* The memory bank addressing translation also needs the original 4327 symbol. */ 4328 case BFD_RELOC_M68HC11_LO16: 4329 case BFD_RELOC_M68HC11_PAGE: 4330 case BFD_RELOC_M68HC11_24: 4331 return 0; 4332 4333 default: 4334 return 1; 4335 } 4336 } 4337 4338 void 4339 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) 4340 { 4341 char *where; 4342 long value = * valP; 4343 4344 if (fixP->fx_addsy == (symbolS *) NULL) 4345 fixP->fx_done = 1; 4346 4347 /* We don't actually support subtracting a symbol. */ 4348 if (fixP->fx_subsy != (symbolS *) NULL) 4349 as_bad_where (fixP->fx_file, fixP->fx_line, _("Expression too complex.")); 4350 4351 /* Patch the instruction with the resolved operand. Elf relocation 4352 info will also be generated to take care of linker/loader fixups. 4353 The 68HC11 addresses only 64Kb, we are only concerned by 8 and 16-bit 4354 relocs. BFD_RELOC_8 is basically used for .page0 access (the linker 4355 will warn for overflows). BFD_RELOC_8_PCREL should not be generated 4356 because it's either resolved or turned out into non-relative insns (see 4357 relax table, bcc, bra, bsr transformations) 4358 4359 The BFD_RELOC_32 is necessary for the support of --gstabs. */ 4360 where = fixP->fx_frag->fr_literal + fixP->fx_where; 4361 4362 switch (fixP->fx_r_type) 4363 { 4364 case BFD_RELOC_32: 4365 bfd_putb32 ((bfd_vma) value, (unsigned char *) where); 4366 break; 4367 4368 case BFD_RELOC_24: 4369 case BFD_RELOC_M68HC11_24: 4370 bfd_putb16 ((bfd_vma) (value & 0x0ffff), (unsigned char *) where); 4371 ((bfd_byte*) where)[2] = ((value >> 16) & 0x0ff); 4372 break; 4373 4374 case BFD_RELOC_16: 4375 case BFD_RELOC_16_PCREL: 4376 case BFD_RELOC_M68HC11_LO16: 4377 bfd_putb16 ((bfd_vma) value, (unsigned char *) where); 4378 if (value < -65537 || value > 65535) 4379 as_bad_where (fixP->fx_file, fixP->fx_line, 4380 _("Value out of 16-bit range.")); 4381 break; 4382 4383 case BFD_RELOC_M68HC11_HI8: 4384 /* Caution, %hi(<symbol>+%ld) will generate incorrect code if %lo 4385 causes a carry. */ 4386 case BFD_RELOC_M68HC12_HI8XG: 4387 value = value >> 8; 4388 /* Fall through. */ 4389 4390 case BFD_RELOC_M68HC12_LO8XG: 4391 case BFD_RELOC_M68HC11_LO8: 4392 case BFD_RELOC_8: 4393 case BFD_RELOC_M68HC11_PAGE: 4394 ((bfd_byte *) where)[0] = (bfd_byte) value; 4395 break; 4396 4397 case BFD_RELOC_8_PCREL: 4398 ((bfd_byte *) where)[0] = (bfd_byte) value; 4399 4400 if (value < -128 || value > 127) 4401 as_bad_where (fixP->fx_file, fixP->fx_line, 4402 _("Value %ld too large for 8-bit PC-relative branch."), 4403 value); 4404 break; 4405 4406 /* These next two are for XGATE. */ 4407 case BFD_RELOC_M68HC12_9_PCREL: 4408 ((bfd_byte *) where)[0] |= (bfd_byte) ((value >>9) & 0x01); 4409 ((bfd_byte *) where)[1] = (bfd_byte) ((value>>1) & 0xff); 4410 if (value < -512 || value > 511) 4411 as_bad_where (fixP->fx_file, fixP->fx_line, 4412 _("Value %ld too large for 9-bit PC-relative branch."), 4413 value); 4414 break; 4415 4416 case BFD_RELOC_M68HC12_10_PCREL: 4417 ((bfd_byte *) where)[0] |= (bfd_byte) ((value >>9) & 0x03); 4418 ((bfd_byte *) where)[1] = (bfd_byte) ((value>>1) & 0xff); 4419 if (value < -1024 || value > 1023) 4420 as_bad_where (fixP->fx_file, fixP->fx_line, 4421 _("Value %ld too large for 10-bit PC-relative branch."), 4422 value); 4423 4424 break; 4425 4426 case BFD_RELOC_M68HC11_3B: 4427 if (value <= 0 || value > 8) 4428 as_bad_where (fixP->fx_file, fixP->fx_line, 4429 _("Auto increment/decrement offset '%ld' is out of range."), 4430 value); 4431 if (where[0] & 0x8) 4432 value = 8 - value; 4433 else 4434 value--; 4435 4436 where[0] = where[0] | (value & 0x07); 4437 break; 4438 4439 case BFD_RELOC_M68HC12_5B: 4440 if (value < -16 || value > 15) 4441 as_bad_where (fixP->fx_file, fixP->fx_line, 4442 _("Offset out of 5-bit range for movw/movb insn: %ld"), 4443 value); 4444 if (value >= 0) 4445 where[0] |= value; 4446 else 4447 where[0] |= (0x10 | (16 + value)); 4448 break; 4449 4450 case BFD_RELOC_M68HC12_9B: 4451 if (value < -256 || value > 255) 4452 as_bad_where (fixP->fx_file, fixP->fx_line, 4453 _("Offset out of 9-bit range for movw/movb insn: %ld"), 4454 value); 4455 /* sign bit already in xb postbyte */ 4456 if (value >= 0) 4457 where[1] = value; 4458 else 4459 where[1] = (256 + value); 4460 break; 4461 4462 case BFD_RELOC_M68HC12_16B: 4463 if (value < -32768 || value > 32767) 4464 as_bad_where (fixP->fx_file, fixP->fx_line, 4465 _("Offset out of 16-bit range for movw/movb insn: %ld"), 4466 value); 4467 if (value < 0) 4468 value += 65536; 4469 4470 where[0] = (value >> 8); 4471 where[1] = (value & 0xff); 4472 break; 4473 4474 case BFD_RELOC_M68HC11_RL_JUMP: 4475 case BFD_RELOC_M68HC11_RL_GROUP: 4476 case BFD_RELOC_VTABLE_INHERIT: 4477 case BFD_RELOC_VTABLE_ENTRY: 4478 fixP->fx_done = 0; 4479 return; 4480 4481 default: 4482 as_fatal (_("Line %d: unknown relocation type: 0x%x."), 4483 fixP->fx_line, fixP->fx_r_type); 4484 } 4485 } 4486 4487 /* Set the ELF specific flags. */ 4488 void 4489 m68hc11_elf_final_processing (void) 4490 { 4491 if (current_architecture & cpu6812s) 4492 elf_flags |= EF_M68HCS12_MACH; 4493 elf_elfheader (stdoutput)->e_flags &= ~EF_M68HC11_ABI; 4494 elf_elfheader (stdoutput)->e_flags |= elf_flags; 4495 } 4496 4497 /* Process directives specified via pseudo ops */ 4498 static void 4499 s_m68hc11_parse_pseudo_instruction (int pseudo_insn) 4500 { 4501 switch (pseudo_insn) 4502 { 4503 case E_M68HC11_NO_BANK_WARNING: 4504 elf_flags |= E_M68HC11_NO_BANK_WARNING; 4505 break; 4506 default: 4507 as_bad (_("Invalid directive")); 4508 } 4509 } 4510
