/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
x86-64-specific-reg.s | 5 .irp reg1, ax, cx, dx, bx, sp, bp, si, di 6 lodsb %ds:(%r\reg1) 8 stosb %es:(%r\reg1) 10 scasb %es:(%r\reg1) 12 insb %dx, %es:(%r\reg1) 14 outsb %ds:(%r\reg1), %dx 16 xlatb %ds:(%r\reg1) 18 movsb %ds:(%r\reg1), %es:(%rdi) 19 movsb %ds:(%rsi), %es:(%r\reg1) 21 cmpsb %es:(%r\reg1), %ds:(%rsi [all...] |
/external/libavc/common/armv8/ |
ih264_neon_macros.s | 36 .macro swp reg1, reg2 37 eor \reg1, \reg1, \reg2 38 eor \reg2, \reg1, \reg2 39 eor \reg1, \reg1, \reg2
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/external/libmpeg2/common/armv8/ |
impeg2_neon_macros.s | 53 .macro swp reg1, reg2 54 eor \reg1, \reg1, \reg2 55 eor \reg2, \reg1, \reg2 56 eor \reg1, \reg1, \reg2
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/external/llvm/test/MC/MachO/ |
bad-macro.s | 5 .macro test_macro reg1, reg2
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/external/libvpx/libvpx/vpx_dsp/mips/ |
idct32x32_msa.c | 44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); 50 DOTP_CONST_PAIR(reg1, reg7, cospi_28_64, cospi_4_64, reg1, reg7); 52 BUTTERFLY_4(reg1, reg7, reg3, reg5, vec1, vec3, vec2, vec0); 65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); 69 DOTP_CONST_PAIR(reg6, reg1, cospi_6_64, cospi_26_64, reg6, reg1); 75 reg2 = reg1 + reg5; 76 reg1 = reg1 - reg5 128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 354 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 434 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local [all...] |
idct16x16_msa.c | 16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; local 19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); 23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1, 40 DOTP_CONST_PAIR(reg1, reg15, cospi_30_64, cospi_2_64, reg1, reg15); 43 reg9 = reg1 - loc2; 44 reg1 = reg1 + loc2; 57 loc1 = reg1 + reg13 110 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; local [all...] |
/art/runtime/interpreter/mterp/arm64/ |
header.S | 299 .macro SAVE_TWO_REGS reg1, reg2, offset 300 stp \reg1, \reg2, [sp, #(\offset)] 301 .cfi_rel_offset \reg1, (\offset) 308 .macro RESTORE_TWO_REGS reg1, reg2, offset 309 ldp \reg1, \reg2, [sp, #(\offset)] 310 .cfi_restore \reg1 317 .macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment 318 stp \reg1, \reg2, [sp, #-(\frame_adjustment)]! 320 .cfi_rel_offset \reg1, 0 327 .macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustmen [all...] |
/toolchain/binutils/binutils-2.25/gas/config/ |
tc-microblaze.c | 894 unsigned reg1; local 939 op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ 943 reg1 = 0; 961 if (check_spl_reg (& reg1)) 971 inst |= (reg1 << RD_LOW) & RD_MASK; 977 inst |= (reg1 << RD_LOW) & RD_MASK; 986 op_end = parse_reg (op_end + 1, ®1); /* Get rd. */ 990 reg1 = 0; 1005 if (check_spl_reg (& reg1)) 1053 count = 32 - reg1; [all...] |
tc-m68hc11.c | 147 register_id reg1; member in struct:operand 1159 oper->reg1 = REG_NONE; 1238 oper->reg1 = reg; [all...] |
/device/linaro/bootloader/arm-trusted-firmware/bl32/tsp/aarch64/ |
tsp_entrypoint.S | 56 .macro save_eret_context reg1 reg2 57 mrs \reg1, elr_el1 59 stp \reg1, \reg2, [sp, #-0x10]! 63 .macro restore_eret_context reg1 reg2 65 ldp \reg1, \reg2, [sp], #0x10 66 msr elr_el1, \reg1
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/external/libunwind/src/ptrace/ |
_UPT_access_mem.c | 63 long reg1, reg2; 64 reg1 = ptrace (PTRACE_PEEKDATA, pid, (void*) (uintptr_t) addr, 0); 70 *val = ((unw_word_t)(reg2) << 32) | (uint32_t) reg1;
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/external/boringssl/src/crypto/perlasm/ |
x86gas.pl | 77 { my($addr,$reg1,$reg2,$idx)=@_; 80 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; } 86 $reg1 = "%$reg1" if ($reg1); 93 $ret .= "($reg1,$reg2,$idx)"; 95 elsif ($reg1) 96 { $ret .= "($reg1)"; }
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x86masm.pl | 46 { my($size,$addr,$reg1,$reg2,$idx)=@_; 49 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; } 68 $ret .= "+$reg1" if ($reg1 ne ""); 71 { $ret .= "$reg1"; }
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x86nasm.pl | 43 { my($size,$addr,$reg1,$reg2,$idx)=@_; 46 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; } 69 $ret .= "+$reg1" if ($reg1 ne ""); 72 { $ret .= "$reg1"; }
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/external/webrtc/webrtc/system_wrappers/include/ |
asm_defines.h | 59 .macro streqh reg1, reg2, num 60 strheq \reg1, \reg2, \num variable
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/device/linaro/bootloader/arm-trusted-firmware/plat/hikey/drivers/ |
hisi_dvfs.c | 215 unsigned int reg1 = 0; local 350 reg1 = read_reg_mask(PMCTRL_ACPUDESTVOL, 0x7F, 358 } while((reg0 != reg1) || (0x1 != reg2)); 373 reg1 = read_reg_mask(PMCTRL_ACPUCLKDIV, 0x3, 381 } while((cpuext_cfg_val != reg1) || 425 unsigned int reg1 = 0; local 598 reg1 = read_reg_mask(PMCTRL_ACPUCLKDIV, 0x3, 604 } while((cpuext_cfg_val != reg0) || (acpu_ddr_cfg_val != reg1)); 634 reg1 = read_reg_mask(PMCTRL_ACPUDESTVOL, 0x7F, 642 } while((reg0 != reg1) || (0x1 != reg2)) [all...] |
/external/libyuv/files/source/ |
row_msa.cc | 481 v16u8 reg0, reg1, reg2, reg3; local 509 reg1 = (v16u8)__msa_sldi_b((v16i8)reg2, (v16i8)reg0, 11); 511 dst1 = (v16u8)__msa_vshf_b(shuffler1, (v16i8)reg3, (v16i8)reg1); 570 v8u16 reg0, reg1, reg2; local 586 reg1 = (v8u16)__msa_srai_h(vec1, 4); 588 reg1 = (v8u16)__msa_slli_h((v8i16)reg1, 4); 590 reg1 |= const_0xF000; 592 dst0 = (v16u8)(reg1 | reg0); 610 v8u16 reg0, reg1, reg2 local 774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local 826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; local 1085 v16u8 src0, src1, src2, src3, reg0, reg1, reg2, reg3, dst0, dst1; local 1159 v4u32 reg0, reg1, reg2, reg3; local 1237 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 1305 v8i16 reg0, reg1, reg2; local 1373 v4u32 reg0, reg1, reg2, reg3, rgba_scale; local 1433 v8u16 reg0, reg1, reg2; local 1506 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6; local 1553 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local 1648 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local 1705 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local 1767 v16u8 src0, src1, src2, reg0, reg1, reg2, reg3, dst0; local 1808 v16u8 src0, src1, src2, reg0, reg1, reg2, reg3, dst0; local 1856 v8u16 src0, src1, src2, src3, reg0, reg1, reg2, reg3; local 1937 v8u16 src0, src1, src2, src3, reg0, reg1, reg2, reg3; local 2020 v8i16 reg0, reg1, reg2, reg3; local 2125 v8i16 reg0, reg1, reg2, reg3; local 2385 v16u8 reg0, reg1, dst0, dst1, dst2, dst3; local 2666 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; local 2729 v4i32 reg0, reg1, reg2, reg3; local [all...] |
rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 99 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); 110 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); 121 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); 137 res8 = (v16u8)__msa_ilvr_w((v4i32)reg5, (v4i32)reg1); 138 res9 = (v16u8)__msa_ilvl_w((v4i32)reg5, (v4i32)reg1); 166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local 180 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3); 191 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); 202 ILVRL_H(vec0, vec2, vec1, vec3, reg0, reg1, reg2, reg3) [all...] |
/toolchain/binutils/binutils-2.25/gas/ |
dw2gencfi.c | 411 cfi_add_CFA_insn_reg_reg (int insn, unsigned reg1, unsigned reg2) 416 insn_ptr->u.rr.reg1 = reg1; 472 cfi_add_CFA_register (unsigned reg1, unsigned reg2) 474 cfi_add_CFA_insn_reg_reg (DW_CFA_register, reg1, reg2); 657 unsigned reg1, reg2; 675 reg1 = cfi_parse_reg (); 678 cfi_add_CFA_offset (reg1, offset); 682 reg1 = cfi_parse_reg (); 685 cfi_add_CFA_offset (reg1, 655 unsigned reg1, reg2; local [all...] |
dw2gencfi.h | 77 unsigned reg1; member in struct:cfi_insn_data::__anon115825::__anon115827
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/external/v8/src/interpreter/ |
bytecode-register.cc | 107 bool Register::AreContiguous(Register reg1, Register reg2, Register reg3, 109 if (reg1.index() + 1 != reg2.index()) {
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/external/mesa3d/src/util/ |
register_allocate.c | 234 struct ra_reg *reg1 = ®s->regs[r1]; local 236 if (reg1->conflict_list) { 237 if (reg1->conflict_list_size == reg1->num_conflicts) { 238 reg1->conflict_list_size *= 2; 239 reg1->conflict_list = reralloc(regs->regs, reg1->conflict_list, 240 unsigned int, reg1->conflict_list_size); 242 reg1->conflict_list[reg1->num_conflicts++] = r2 [all...] |
/art/compiler/utils/ |
assembler_test.h | 144 template <typename Reg1, typename Reg2, typename ImmType> 145 std::string RepeatTemplatedRegistersImmBits(void (Ass::*f)(Reg1, Reg2, ImmType), 147 const std::vector<Reg1*> reg1_registers, 149 std::string (AssemblerTest::*GetName1)(const Reg1&), 157 for (auto reg1 : reg1_registers) { 161 (assembler_.get()->*f)(*reg1, *reg2, new_imm * multiplier + bias); 164 std::string reg1_string = (this->*GetName1)(*reg1); 196 template <typename Reg1, typename Reg2, typename Reg3, typename ImmType> 197 std::string RepeatTemplatedRegistersImmBits(void (Ass::*f)(Reg1, Reg2, Reg3, ImmType), 199 const std::vector<Reg1*> reg1_registers [all...] |
/external/v8/src/compiler/mips64/ |
code-generator-mips64.cc | 1040 Register reg1 = kScratchReg; local 1060 Register reg1 = kScratchReg; local 1080 Register reg1 = kScratchReg; local 1124 Register reg1 = kScratchReg; local [all...] |
/art/compiler/utils/arm/ |
assembler_arm_test.h | 77 template <typename Reg1, typename Reg2> 78 std::string RepeatTemplatedRRIIC(void (Ass::*f)(Reg1, Reg2, Imm, Imm, Cond), 79 const std::vector<Reg1*> reg1_registers, 81 std::string (AssemblerArmTest::*GetName1)(const Reg1&), 128 for (auto reg1 : reg1_registers) { 131 std::string reg1_string = (this->*GetName1)(*reg1); 153 (Base::GetAssembler()->*f)(*reg1, *reg2, i, j, c); 174 template <typename Reg1, typename Reg2> 175 std::string RepeatTemplatedRRiiC(void (Ass::*f)(Reg1, Reg2, Imm, Imm, Cond), 176 const std::vector<Reg1*> reg1_registers [all...] |