/art/compiler/linker/arm/ |
relative_patcher_thumb2_test.cc | 268 void TestBakerFieldWide(uint32_t offset, uint32_t ref_reg); 269 void TestBakerFieldNarrow(uint32_t offset, uint32_t ref_reg); 578 void Thumb2RelativePatcherTest::TestBakerFieldWide(uint32_t offset, uint32_t ref_reg) { 590 uint32_t ldr = kLdrWInsn | offset | (base_reg << 16) | (ref_reg << 12); 612 uint32_t ldr = kLdrWInsn | offset | (base_reg << 16) | (ref_reg << 12); 677 void Thumb2RelativePatcherTest::TestBakerFieldNarrow(uint32_t offset, uint32_t ref_reg) { 692 uint32_t ldr = kLdrInsn | (offset << (6 - 2)) | (base_reg << 3) | ref_reg; 717 uint32_t ldr = kLdrInsn | (offset << (6 - 2)) | (base_reg << 3) | ref_reg; [all...] |
/art/compiler/linker/arm64/ |
relative_patcher_arm64_test.cc | 505 void TestBakerField(uint32_t offset, uint32_t ref_reg); [all...] |
/art/compiler/optimizing/ |
code_generator_mips64.cc | 564 GpuRegister ref_reg = ref_.AsRegister<GpuRegister>(); variable 566 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(ref_reg)) << ref_reg; 585 DCHECK((V0 <= ref_reg && ref_reg <= T2) || 586 (S2 <= ref_reg && ref_reg <= S7) || 587 (ref_reg == S8)) << ref_reg; 609 Thread::ReadBarrierMarkEntryPointsOffset<kMips64PointerSize>(ref_reg - 1) 659 GpuRegister ref_reg = ref_.AsRegister<GpuRegister>(); variable [all...] |
code_generator_arm_vixl.cc | 758 vixl32::Register ref_reg = RegisterFrom(ref_); local 764 DCHECK(!ref_reg.Is(sp)); 765 DCHECK(!ref_reg.Is(lr)); 766 DCHECK(!ref_reg.Is(pc)); 769 DCHECK(!ref_reg.Is(ip)); 770 DCHECK(ref_reg.IsRegister()) << ref_reg; 791 Thread::ReadBarrierMarkEntryPointsOffset<kArmPointerSize>(ref_reg.GetCode()); 898 vixl32::Register ref_reg = RegisterFrom(ref_); variable 1050 vixl32::Register ref_reg = RegisterFrom(ref_); variable 8672 vixl32::Register ref_reg = RegisterFrom(ref, Primitive::kPrimNot); local 8708 __ rsbs(EncodingSize(Narrow), ref_reg, ref_reg, Operand(0)); local 8710 __ rsb(EncodingSize(Wide), ref_reg, ref_reg, Operand(0)); local 8766 vixl32::Register ref_reg = RegisterFrom(ref, Primitive::kPrimNot); local 8789 __ rsb(EncodingSize(Wide), ref_reg, ref_reg, Operand(0)); local 8911 vixl32::Register ref_reg = RegisterFrom(ref, type); local [all...] |
code_generator_mips.cc | 614 Register ref_reg = ref_.AsRegister<Register>(); variable 616 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(ref_reg)) << ref_reg; 635 DCHECK((V0 <= ref_reg && ref_reg <= T7) || 636 (S2 <= ref_reg && ref_reg <= S7) || 637 (ref_reg == FP)) << ref_reg; 659 Thread::ReadBarrierMarkEntryPointsOffset<kMipsPointerSize>(ref_reg - 1) 710 Register ref_reg = ref_.AsRegister<Register>(); variable 6604 Register ref_reg = ref.AsRegister<Register>(); local [all...] |
code_generator_arm64.cc | 990 Register ref_reg = WRegisterFrom(ref_); variable [all...] |
code_generator_x86.cc | 471 Register ref_reg = ref_.AsRegister<Register>(); variable 473 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(ref_reg)) << ref_reg; 490 __ MaybeUnpoisonHeapReference(ref_reg); 496 DCHECK_NE(ref_reg, ESP); 497 DCHECK(0 <= ref_reg && ref_reg < kNumberOfCpuRegisters) << ref_reg; 512 int32_t entry_point_offset = Thread::ReadBarrierMarkEntryPointsOffset<kX86PointerSize>(ref_reg); 558 Register ref_reg = ref_.AsRegister<Register>() variable 7247 Register ref_reg = ref.AsRegister<Register>(); local [all...] |
code_generator_x86_64.cc | 485 Register ref_reg = ref_cpu_reg.AsRegister(); variable 487 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(ref_reg)) << ref_reg; 510 DCHECK_NE(ref_reg, RSP); 511 DCHECK(0 <= ref_reg && ref_reg < kNumberOfCpuRegisters) << ref_reg; 527 Thread::ReadBarrierMarkEntryPointsOffset<kX86_64PointerSize>(ref_reg); 578 Register ref_reg = ref_cpu_reg.AsRegister(); variable 580 DCHECK(!locations->GetLiveRegisters()->ContainsCoreRegister(ref_reg)) << ref_reg 6637 CpuRegister ref_reg = ref.AsRegister<CpuRegister>(); local [all...] |
/art/compiler/utils/arm64/ |
jni_macro_assembler_arm64.cc | 308 WRegister ref_reg = dst.AsOverlappingWRegister(); local 309 asm_.MaybeUnpoisonHeapReference(reg_w(ref_reg));
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