| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| smartmips.s | 8 rotrv $4,$5,$6
|
| mips32r2.s | 39 rotrv $25, $10, $4
|
| /external/llvm/test/MC/Mips/ |
| micromips-shift-instructions.s | 17 # CHECK-EL: rotrv $9, $6, $7 # encoding: [0xc7,0x00,0xd0,0x48]
37 # CHECK-EB: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
54 rotrv $9, $6, $7
|
| rotations32.s | 15 # CHECK-32R: rotrv $4, $4, $1 # encoding: [0x00,0x24,0x20,0x46]
22 # CHECK-32R: rotrv $4, $5, $4 # encoding: [0x00,0x85,0x20,0x46]
55 # CHECK-32R: rotrv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x46]
61 # CHECK-32R: rotrv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x46]
|
| mips-alu-instructions.s | 20 # CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00]
51 rotrv $9, $6, $7
|
| mips64-alu-instructions.s | 18 # CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00]
46 rotrv $9, $6, $7
|
| rotations64.s | 15 # CHECK-64R: rotrv $4, $4, $1 # encoding: [0x00,0x24,0x20,0x46]
22 # CHECK-64R: rotrv $4, $5, $4 # encoding: [0x00,0x85,0x20,0x46]
55 # CHECK-64R: rotrv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x46]
61 # CHECK-64R: rotrv $4, $5, $6 # encoding: [0x00,0xc5,0x20,0x46]
|
| /bionic/libc/arch-mips/string/ |
| strcmp.S | 277 rotrv v0, v0, t1
278 rotrv v1, v1, t1
|
| strncmp.S | 309 rotrv v0, v0, t1
310 rotrv v1, v1, t1
|
| /external/llvm/test/MC/Mips/mips32/ |
| invalid-mips32r2.s | 30 rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips64r2.s | 36 rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64/ |
| invalid-mips64r2.s | 28 rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32r2.s | 62 rotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| valid.s | 168 rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| valid.s | 168 rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| valid.s | 169 rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
|
| /external/llvm/test/MC/Mips/micromips/ |
| invalid.s | 46 rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 235 rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 235 rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 236 rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| valid.s | 48 rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
|
| invalid.s | 235 rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| valid.s | 87 rotrv $9, $6, $7 # CHECK: rotrv $9, $6, $7 # encoding: [0x00,0xc7,0x48,0xd0]
[all...] |
| invalid.s | 203 rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/v8/src/mips/ |
| disasm-mips.cc | 1082 Format(instr, "rotrv 'rd, 'rt, 'rs");
[all...] |
