1 # RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=micromips 2>%t1 2 # RUN: FileCheck %s < %t1 3 4 addiur1sp $7, 260 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4 5 addiur1sp $7, 241 # CHECK: :[[@LINE]]:17: error: expected both 8-bit unsigned immediate and multiple of 4 6 addiur1sp $8, 240 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction 7 addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 8 addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 9 addius5 $2, -9 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate 10 addius5 $2, 8 # CHECK: :[[@LINE]]:15: error: expected 4-bit signed immediate 11 addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 12 align $4, $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate 13 align $4, $2, $3, 4 # CHECK: :[[@LINE]]:21: error: expected 2-bit unsigned immediate 14 beqzc16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 15 beqzc16 $6, 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 16 beqzc16 $6, 130 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 17 bnezc16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 18 bnezc16 $6, 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 19 bnezc16 $6, 130 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 20 break -1 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate 21 break 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate 22 break -1, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate 23 break 1024, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate 24 break 7, -1 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate 25 break 7, 1024 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate 26 break 1023, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate 27 cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate 28 cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate 29 # FIXME: Check '0 < pos + size <= 32' constraint on ext 30 ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 31 ext $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 32 ext $2, $3, 1, 0 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32 33 ext $2, $3, 1, 33 # CHECK: :[[@LINE]]:18: error: expected immediate in range 1 .. 32 34 ins $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 35 ins $2, $3, 32, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 36 ei $32 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 37 swe $33, 8($4) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction 38 # FIXME: This ought to point at the $34 but memory is treated as one operand. 39 swe $5, 8($34) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 40 swe $5, 512($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 41 lbu16 $9, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 42 lbu16 $3, -2($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 43 lbu16 $3, -2($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 44 lbu16 $16, 8($9) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 45 lhu16 $9, 4($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 46 lhu16 $3, 64($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 47 lhu16 $3, 64($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 48 lhu16 $16, 4($9) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 49 li16 $4, -2 # CHECK: :[[@LINE]]:12: error: expected immediate in range -1 .. 126 50 li16 $4, 127 # CHECK: :[[@LINE]]:12: error: expected immediate in range -1 .. 126 51 lsa $4, $2, $3, 0 # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 4 52 lsa $4, $2, $3, 5 # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 4 53 lw16 $9, 8($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 54 lw16 $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 55 lw16 $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 56 lw16 $17, 8($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 57 pref -1, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate 58 pref 32, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate 59 teq $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 60 teq $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 61 tge $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 62 tge $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 63 tgeu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 64 tgeu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 65 tlt $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 66 tlt $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 67 tltu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 68 tltu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 69 tne $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 70 tne $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 71 wait -1 # CHECK: :[[@LINE]]:8: error: expected 10-bit unsigned immediate 72 wait 1024 # CHECK: :[[@LINE]]:8: error: expected 10-bit unsigned immediate 73 wrpgpr $34, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 74 wrpgpr $3, $33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 75 wsbh $34, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 76 wsbh $3, $33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 77 jrcaddiusp 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 78 jrcaddiusp 2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 79 jrcaddiusp 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 80 jrcaddiusp 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 81 jrcaddiusp 18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 82 jrcaddiusp 31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 83 jrcaddiusp 33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 84 jrcaddiusp 125 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 85 jrcaddiusp 132 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4 86 lwm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected 87 lwm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected 88 lwm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand 89 lwm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 90 lwm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 91 lwm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 92 lwm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 93 lwm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 94 sb16 $9, 4($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 95 sb16 $3, 64($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 96 sb16 $16, 4($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 97 sb16 $7, 4($9) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 98 sh16 $9, 8($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 99 sh16 $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 100 sh16 $16, 8($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 101 sh16 $7, 8($9) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 102 sync -1 # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate 103 sync 32 # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate 104 sw16 $9, 4($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 105 sw16 $4, 64($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range 106 sw16 $16, 4($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 107 sw16 $7, 4($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 108 swm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected 109 swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected 110 swm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand 111 swm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 112 swm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 113 swm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 114 swm16 $16, $17, $ra, 8($fp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 115 swm16 $16, $17, $ra, 64($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 116 mtc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate 117 mtc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate 118 mthc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate 119 mthc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate 120 mfc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate 121 mfc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate 122 mfhc0 $4, $3, -1 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate 123 mfhc0 $4, $3, 8 # CHECK: :[[@LINE]]:17: error: expected 3-bit unsigned immediate 124 tlbp $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 125 tlbp 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 126 tlbp $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 127 tlbr $3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 128 tlbr 5 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 129 tlbr $4, 6 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 130 tlbwi $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction 131 tlbwi 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction 132 tlbwi $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction 133 tlbwr $3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction 134 tlbwr 5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction 135 tlbwr $4, 6 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction 136 dvp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction 137 dvp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction 138 evp 3 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction 139 evp $4, 5 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction 140 jalrc.hb $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different 141 jalrc.hb $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different 142 sll $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 143 sll $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 144 sra $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 145 sra $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 146 srl $4, $3, -1 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 147 srl $4, $3, 32 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate 148 sll $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate 149 sll $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate 150 sra $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate 151 sra $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate 152 srl $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate 153 srl $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate 154 lle $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction 155 lle $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 156 lle $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 157 lle $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 158 lwe $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction 159 lwe $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 160 lwe $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 161 lwe $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 162 sbe $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction 163 sbe $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 164 sbe $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 165 sbe $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 166 sce $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction 167 sce $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 168 sce $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 169 sce $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 170 she $33, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction 171 she $4, 8($33) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 172 she $4, 512($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 173 she $4, -513($5) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 174 swe $5, -513($4) # CHECK: :[[@LINE]]:11: error: expected memory with 9-bit signed offset 175 lh $33, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 176 lhe $34, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 177 lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 178 lhue $36, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 179 lh $2, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset 180 lhe $4, 8($33) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset 181 lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset 182 lhue $4, 8($37) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset 183 lh $2, -65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset 184 lh $2, 65536($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset 185 lhe $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset 186 lhe $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset 187 lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset 188 lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset 189 lhue $4, -512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset 190 lhue $4, 512($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset 191 lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected 192 lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected 193 lwm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand 194 lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $24, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand 195 movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 196 movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 197 movep $5, $21, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 198 movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 199 rotr $2, -1 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate 200 rotr $2, 32 # CHECK: :[[@LINE]]:12: error: expected 5-bit unsigned immediate 201 rotr $2, $3, -1 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate 202 rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate 203 rotrv $9, $6, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 204 swm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected 205 swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected 206 swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand 207 lwp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 208 # FIXME: This ought to point at the $34 but memory is treated as one operand. 209 lwp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset 210 lwp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset 211 lwp $16, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different 212 swp $31, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 213 swp $16, 8($34) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset 214 swp $16, 4096($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 12-bit signed offset 215 # bposge32 is microMIPS DSP instruction 216 bposge32 342 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 217 bc1eqzc $f32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction 218 bc1eqzc $f31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 219 bc1eqzc $f31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 220 bc1eqzc $f31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 221 bc1eqzc $f31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 222 bc1nezc $f32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction 223 bc1nezc $f31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 224 bc1nezc $f31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 225 bc1nezc $f31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 226 bc1nezc $f31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 227 bc2eqzc $32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction 228 bc2eqzc $31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 229 bc2eqzc $31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 230 bc2eqzc $31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 231 bc2eqzc $31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 232 bc2nezc $32, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction 233 bc2nezc $31, -65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 234 bc2nezc $31, -65537 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 235 bc2nezc $31, 65535 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch to misaligned address 236 bc2nezc $31, 65536 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: branch target out of range 237 jalrc $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different 238 jalrc $31, $31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: source and destination must be different 239 andi $3, $4, -1 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate 240 andi $3, $4, 65536 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate 241 andi $3, -1 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate 242 andi $3, 65536 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate 243 ori $3, $4, -1 # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate 244 ori $3, $4, 65536 # CHECK: :[[@LINE]]:15: error: expected 16-bit unsigned immediate 245 ori $3, -1 # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate 246 ori $3, 65536 # CHECK: :[[@LINE]]:11: error: expected 16-bit unsigned immediate 247 xori $3, $4, -1 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate 248 xori $3, $4, 65536 # CHECK: :[[@LINE]]:16: error: expected 16-bit unsigned immediate 249 xori $3, -1 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate 250 xori $3, 65536 # CHECK: :[[@LINE]]:12: error: expected 16-bit unsigned immediate 251 not $3, 4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction 252 lb $32, 8($5) # CHECK: :[[@LINE]]:6: error: invalid operand for instruction 253 lb $4, -32769($5) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset 254 lb $4, 32768($5) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset 255 lb $4, 8($32) # CHECK: :[[@LINE]]:10: error: expected memory with 16-bit signed offset 256 lbu $32, 8($5) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction 257 lbu $4, -32769($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset 258 lbu $4, 32768($5) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset 259 lbu $4, 8($32) # CHECK: :[[@LINE]]:11: error: expected memory with 16-bit signed offset 260 ldc1 $f32, 300($10) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 261 ldc1 $f7, -32769($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 262 ldc1 $f7, 32768($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 263 ldc1 $f7, 300($32) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 264 sdc1 $f32, 64($10) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 265 sdc1 $f7, -32769($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 266 sdc1 $f7, 32768($10) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 267 sdc1 $f7, 64($32) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 268 lwc1 $f32, 32($5) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 269 lwc1 $f2, -32769($5) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 270 lwc1 $f2, 32768($5) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 271 lwc1 $f2, 32($32) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 272 swc1 $f32, 369($13) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 273 swc1 $f6, -32769($13) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 274 swc1 $f6, 32768($13) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 275 swc1 $f6, 369($32) # CHECK: :[[@LINE]]:13: error: expected memory with 16-bit signed offset 276 ldc2 $32, 1023($12) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 277 sdc2 $32, 8($16) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 278 lwc2 $32, 16($4) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 279 swc2 $32, 777($17) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction 280 sdc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 281 sdc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 282 swc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 283 swc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 284
