| /art/compiler/optimizing/ |
| code_generator_arm_vixl.cc | 1226 const vixl32::Register temp1_; member in class:art::arm::LoadReferenceWithBakerReadBarrierAndUpdateFieldSlowPathARMVIXL
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| code_generator_mips64.cc | 649 temp1_(temp1) {
676 DCHECK_NE(temp1_, AT);
677 DCHECK_NE(temp1_, TMP);
678 __ Move(temp1_, ref_reg);
716 __ Beqc(temp1_, ref_reg, &done);
727 GpuRegister expected = temp1_;
780 const GpuRegister temp1_; member in class:art::mips64::ReadBarrierMarkAndUpdateFieldSlowPathMIPS64
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| code_generator_mips.cc | 700 temp1_(temp1) {
727 DCHECK_NE(temp1_, AT);
728 DCHECK_NE(temp1_, TMP);
729 __ Move(temp1_, ref_reg);
768 __ Beq(temp1_, ref_reg, &done);
841 const Register temp1_; member in class:art::mips::ReadBarrierMarkAndUpdateFieldSlowPathMIPS
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| code_generator_x86_64.cc | 566 temp1_(temp1),
595 __ movl(temp1_, ref_cpu_reg);
630 __ cmpl(temp1_, ref_cpu_reg);
641 // expected value (stored in `temp1_`) into EAX.
643 __ movl(CpuRegister(RAX), temp1_); variable
657 value_reg = temp1_.AsRegister();
708 const CpuRegister temp1_; member in class:art::x86_64::ReadBarrierMarkAndUpdateFieldSlowPathX86_64
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