/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
trap20.s | 11 tltu $0,$3 12 tltu $0,$3,255
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trap20.d | 16 0+0020 <[^>]*> tltu zero,v1 17 0+0024 <[^>]*> tltu zero,v1,0xff
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micromips.s | [all...] |
/external/llvm/test/MC/Mips/ |
micromips-trap-instructions.s | 16 # CHECK-EL: tltu $8, $9 # encoding: [0x28,0x01,0x3c,0x0a] 31 # CHECK-EB: tltu $8, $9 # encoding: [0x01,0x28,0x0a,0x3c] 43 tltu $8, $9, 0
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mips-control-instructions.s | 30 # CHECK32: tltu $zero, $3 # encoding: [0x00,0x03,0x00,0x33] 31 # CHECK32: tltu $zero, $3, 255 # encoding: [0x00,0x03,0x3f,0xf3] 61 # CHECK64: tltu $zero, $3 # encoding: [0x00,0x03,0x00,0x33] 62 # CHECK64: tltu $zero, $3, 255 # encoding: [0x00,0x03,0x3f,0xf3] 95 tltu $0,$3 96 tltu $0,$3,255
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/external/llvm/test/MC/Mips/micromips32r6/ |
invalid-wrong-error.s | 22 tltu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate 23 tltu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate 24 tltu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
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valid.s | 263 tltu $11, $16 # CHECK: tltu $11, $16 # encoding: [0x02,0x0b,0x0a,0x3c] 264 tltu $16, $sp, 15 # CHECK: tltu $16, $sp, 15 # encoding: [0x03,0xb0,0xfa,0x3c] [all...] |
invalid.s | 67 tltu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 68 tltu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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/external/llvm/test/MC/Mips/micromips64r6/ |
invalid-wrong-error.s | 30 tltu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate 31 tltu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate 32 tltu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
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valid.s | 135 tltu $11, $16 # CHECK: tltu $11, $16 # encoding: [0x02,0x0b,0x0a,0x3c] 136 tltu $16, $sp, 15 # CHECK: tltu $16, $sp, 15 # encoding: [0x03,0xb0,0xfa,0x3c]
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invalid.s | 95 tltu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction 96 tltu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
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/external/llvm/test/MC/Mips/mips1/ |
invalid-mips2.s | 41 tltu $11,$16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 42 tltu $16,$29,1016 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/MC/Mips/mips2/ |
valid.s | 168 tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] 169 tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
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/external/llvm/test/MC/Mips/mips3/ |
valid.s | 232 tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] 233 tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
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/external/llvm/test/MC/Mips/mips32/ |
valid.s | 198 tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] 199 tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
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/external/llvm/test/MC/Mips/mips32r2/ |
valid.s | 235 tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] 236 tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
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/external/llvm/test/MC/Mips/mips32r3/ |
valid.s | 235 tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] 236 tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
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/external/llvm/test/MC/Mips/mips32r5/ |
valid.s | 236 tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] 237 tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
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/external/llvm/test/MC/Mips/mips4/ |
valid.s | 261 tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] 262 tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
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/external/llvm/test/MC/Mips/mips5/ |
valid.s | 263 tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] 264 tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
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/external/llvm/test/MC/Mips/mips64/ |
valid.s | 282 tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] 283 tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
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/external/llvm/test/MC/Mips/mips64r2/ |
valid.s | 308 tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] 309 tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
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/external/llvm/test/MC/Mips/mips64r3/ |
valid.s | 308 tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] 309 tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
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/external/llvm/test/MC/Mips/mips64r5/ |
valid.s | 309 tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] 310 tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
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/external/v8/src/mips/ |
disasm-mips.cc | 431 case TLTU: [all...] |