| /external/llvm/lib/Target/Mips/ |
| MicroMips64r6InstrInfo.td | 136 list<dag> Pattern = [(set GPR64Opnd:$rt, (ctlz (not GPR64Opnd:$rs)))];
146 list<dag> Pattern = [(set GPR64Opnd:$rt, (ctlz GPR64Opnd:$rs))];
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| bitwise.ll | 925 %2 = tail call <16 x i8> @llvm.ctlz.v16i8 (<16 x i8> %1)
939 %2 = tail call <8 x i16> @llvm.ctlz.v8i16 (<8 x i16> %1)
953 %2 = tail call <4 x i32> @llvm.ctlz.v4i32 (<4 x i32> %1)
967 %2 = tail call <2 x i64> @llvm.ctlz.v2i64 (<2 x i64> %1)
[all...] |
| /external/llvm/lib/IR/ |
| AutoUpgrade.cpp | 85 // llvm.ctlz.*
88 "llvm.ctlz." + Name.substr(14), F->getParent());
137 if (Name.startswith("ctlz.") && F->arg_size() == 1) {
139 NewFn = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz,
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineSelect.cpp | 358 /// Attempt to fold a cttz/ctlz followed by a icmp plus select into a single
359 /// call to cttz/ctlz with flag 'is_zero_undef' cleared.
397 // Check that 'Count' is a call to intrinsic cttz/ctlz. Also check that the
398 // input to the cttz/ctlz is used as LHS for the compare instruction.
400 match(Count, m_Intrinsic<Intrinsic::ctlz>(m_Specific(CmpLHS)))) {
[all...] |
| InstCombineShifts.cpp | 756 // ctlz.i32(x)>>5 --> zext(x == 0)
759 if ((II->getIntrinsicID() == Intrinsic::ctlz ||
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 309 setOperationAction(ISD::CTLZ, VT, Expand);
345 setOperationAction(ISD::CTLZ, MVT::i64, Custom);
398 setOperationAction(ISD::CTLZ, VT, Expand);
550 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
723 case ISD::CTLZ:
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 334 setOperationPromotedToType(ISD::CTLZ , MVT::i8 , MVT::i32);
337 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
338 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
344 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
677 setOperationAction(ISD::CTLZ, VT, Expand);
[all...] |
| X86IntrinsicsInfo.h | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | [all...] |
| /external/clang/test/CodeGen/ |
| builtins-systemz-vector.c | 153 // CHECK: call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %{{.*}}, i1 false)
155 // CHECK: call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %{{.*}}, i1 false)
157 // CHECK: call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %{{.*}}, i1 false)
159 // CHECK: call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %{{.*}}, i1 false)
[all...] |
| aarch64-neon-misc.c | [all...] |
| /external/llvm/lib/Analysis/ |
| DemandedBits.cpp | 113 case Intrinsic::ctlz:
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrVector.td | 387 def VCLZB : UnaryVRRa<"vclzb", 0xE753, ctlz, v128b, v128b, 0>;
388 def VCLZH : UnaryVRRa<"vclzh", 0xE753, ctlz, v128h, v128h, 1>;
389 def VCLZF : UnaryVRRa<"vclzf", 0xE753, ctlz, v128f, v128f, 2>;
390 def VCLZG : UnaryVRRa<"vclzg", 0xE753, ctlz, v128g, v128g, 3>;
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| avx512cdvl-intrinsics.ll | 4 declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readonly
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 160 case ISD::CTLZ:
|
| LegalizeIntegerTypes.cpp | 60 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
315 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| BasicTTIImpl.h | 178 if (IID == Intrinsic::ctlz) {
824 // FIXME: ctlz, cttz, ...
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 113 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
114 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 682 // ctlz.i32(x)>>5 --> zext(x == 0)
685 if ((II->getIntrinsicID() == Intrinsic::ctlz ||
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86InstrInfo.td | [all...] |
| /external/llvm/include/llvm/Target/ |
| TargetSelectionDAG.td | 135 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
411 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| TargetSelectionDAG.td | 115 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
352 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-3957855/prebuilt_include/llvm/include/llvm/Target/ |
| TargetSelectionDAG.td | 135 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
419 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-3960126/prebuilt_include/llvm/include/llvm/Target/ |
| TargetSelectionDAG.td | 135 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
419 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-3977809/prebuilt_include/llvm/include/llvm/Target/ |
| TargetSelectionDAG.td | 135 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
419 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
[all...] |
