1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the target-independent interfaces used by SelectionDAG 11 // instruction selection generators. 12 // 13 //===----------------------------------------------------------------------===// 14 15 //===----------------------------------------------------------------------===// 16 // Selection DAG Type Constraint definitions. 17 // 18 // Note that the semantics of these constraints are hard coded into tblgen. To 19 // modify or add constraints, you have to hack tblgen. 20 // 21 22 class SDTypeConstraint<int opnum> { 23 int OperandNum = opnum; 24 } 25 26 // SDTCisVT - The specified operand has exactly this VT. 27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> { 28 ValueType VT = vt; 29 } 30 31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>; 32 33 // SDTCisInt - The specified operand has integer type. 34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>; 35 36 // SDTCisFP - The specified operand has floating-point type. 37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>; 38 39 // SDTCisVec - The specified operand has a vector type. 40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>; 41 42 // SDTCisSameAs - The two specified operands have identical types. 43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 44 int OtherOperandNum = OtherOp; 45 } 46 47 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is 48 // smaller than the 'Other' operand. 49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> { 50 int OtherOperandNum = OtherOp; 51 } 52 53 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{ 54 int BigOperandNum = BigOp; 55 } 56 57 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same 58 /// type as the element type of OtherOp, which is a vector type. 59 class SDTCisEltOfVec<int ThisOp, int OtherOp> 60 : SDTypeConstraint<ThisOp> { 61 int OtherOpNum = OtherOp; 62 } 63 64 /// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type 65 /// with length less that of OtherOp, which is a vector type. 66 class SDTCisSubVecOfVec<int ThisOp, int OtherOp> 67 : SDTypeConstraint<ThisOp> { 68 int OtherOpNum = OtherOp; 69 } 70 71 //===----------------------------------------------------------------------===// 72 // Selection DAG Type Profile definitions. 73 // 74 // These use the constraints defined above to describe the type requirements of 75 // the various nodes. These are not hard coded into tblgen, allowing targets to 76 // add their own if needed. 77 // 78 79 // SDTypeProfile - This profile describes the type requirements of a Selection 80 // DAG node. 81 class SDTypeProfile<int numresults, int numoperands, 82 list<SDTypeConstraint> constraints> { 83 int NumResults = numresults; 84 int NumOperands = numoperands; 85 list<SDTypeConstraint> Constraints = constraints; 86 } 87 88 // Builtin profiles. 89 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'. 90 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'. 91 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'. 92 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'. 93 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'. 94 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert. 95 96 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc. 97 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0> 98 ]>; 99 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl 100 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2> 101 ]>; 102 def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem 103 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0> 104 ]>; 105 106 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc. 107 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0> 108 ]>; 109 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign. 110 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2> 111 ]>; 112 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc. 113 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0> 114 ]>; 115 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz 116 SDTCisSameAs<0, 1>, SDTCisInt<0> 117 ]>; 118 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext 119 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0> 120 ]>; 121 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc 122 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1> 123 ]>; 124 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc 125 SDTCisSameAs<0, 1>, SDTCisFP<0> 126 ]>; 127 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround 128 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> 129 ]>; 130 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend 131 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0> 132 ]>; 133 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp 134 SDTCisFP<0>, SDTCisInt<1> 135 ]>; 136 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int 137 SDTCisInt<0>, SDTCisFP<1> 138 ]>; 139 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg 140 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>, 141 SDTCisVTSmallerThanOp<2, 1> 142 ]>; 143 144 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc 145 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT> 146 ]>; 147 148 def SDTSelect : SDTypeProfile<1, 3, [ // select 149 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 150 ]>; 151 152 def SDTVSelect : SDTypeProfile<1, 3, [ // vselect 153 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3> 154 ]>; 155 156 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc 157 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>, 158 SDTCisVT<5, OtherVT> 159 ]>; 160 161 def SDTBr : SDTypeProfile<0, 1, [ // br 162 SDTCisVT<0, OtherVT> 163 ]>; 164 165 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond 166 SDTCisInt<0>, SDTCisVT<1, OtherVT> 167 ]>; 168 169 def SDTBrind : SDTypeProfile<0, 1, [ // brind 170 SDTCisPtrTy<0> 171 ]>; 172 173 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap 174 175 def SDTLoad : SDTypeProfile<1, 1, [ // load 176 SDTCisPtrTy<1> 177 ]>; 178 179 def SDTStore : SDTypeProfile<0, 2, [ // store 180 SDTCisPtrTy<1> 181 ]>; 182 183 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store 184 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3> 185 ]>; 186 187 def SDTVecShuffle : SDTypeProfile<1, 2, [ 188 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> 189 ]>; 190 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract 191 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2> 192 ]>; 193 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert 194 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3> 195 ]>; 196 197 def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract 198 SDTCisSubVecOfVec<0,1>, SDTCisInt<2> 199 ]>; 200 def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert 201 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3> 202 ]>; 203 204 def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch 205 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1> 206 ]>; 207 208 def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barier 209 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>, 210 SDTCisInt<0> 211 ]>; 212 def SDTAtomicFence : SDTypeProfile<0, 2, [ 213 SDTCisSameAs<0,1>, SDTCisPtrTy<0> 214 ]>; 215 def SDTAtomic3 : SDTypeProfile<1, 3, [ 216 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1> 217 ]>; 218 def SDTAtomic2 : SDTypeProfile<1, 2, [ 219 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1> 220 ]>; 221 def SDTAtomicStore : SDTypeProfile<0, 2, [ 222 SDTCisPtrTy<0>, SDTCisInt<1> 223 ]>; 224 def SDTAtomicLoad : SDTypeProfile<1, 1, [ 225 SDTCisInt<0>, SDTCisPtrTy<1> 226 ]>; 227 228 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su 229 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5> 230 ]>; 231 232 class SDCallSeqStart<list<SDTypeConstraint> constraints> : 233 SDTypeProfile<0, 1, constraints>; 234 class SDCallSeqEnd<list<SDTypeConstraint> constraints> : 235 SDTypeProfile<0, 2, constraints>; 236 237 //===----------------------------------------------------------------------===// 238 // Selection DAG Node Properties. 239 // 240 // Note: These are hard coded into tblgen. 241 // 242 class SDNodeProperty; 243 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X 244 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z) 245 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result 246 def SDNPOutGlue : SDNodeProperty; // Write a flag result 247 def SDNPInGlue : SDNodeProperty; // Read a flag operand 248 def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand 249 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'. 250 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'. 251 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'. 252 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand 253 def SDNPVariadic : SDNodeProperty; // Node has variable arguments. 254 def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match 255 def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent 256 257 //===----------------------------------------------------------------------===// 258 // Selection DAG Pattern Operations 259 class SDPatternOperator; 260 261 //===----------------------------------------------------------------------===// 262 // Selection DAG Node definitions. 263 // 264 class SDNode<string opcode, SDTypeProfile typeprof, 265 list<SDNodeProperty> props = [], string sdclass = "SDNode"> 266 : SDPatternOperator { 267 string Opcode = opcode; 268 string SDClass = sdclass; 269 list<SDNodeProperty> Properties = props; 270 SDTypeProfile TypeProfile = typeprof; 271 } 272 273 // Special TableGen-recognized dag nodes 274 def set; 275 def implicit; 276 def node; 277 def srcvalue; 278 279 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">; 280 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">; 281 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">; 282 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">; 283 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">; 284 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">; 285 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>; 286 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [], 287 "GlobalAddressSDNode">; 288 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [], 289 "GlobalAddressSDNode">; 290 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [], 291 "GlobalAddressSDNode">; 292 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [], 293 "GlobalAddressSDNode">; 294 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [], 295 "ConstantPoolSDNode">; 296 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [], 297 "ConstantPoolSDNode">; 298 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [], 299 "JumpTableSDNode">; 300 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [], 301 "JumpTableSDNode">; 302 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [], 303 "FrameIndexSDNode">; 304 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [], 305 "FrameIndexSDNode">; 306 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [], 307 "ExternalSymbolSDNode">; 308 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [], 309 "ExternalSymbolSDNode">; 310 def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [], 311 "BlockAddressSDNode">; 312 def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [], 313 "BlockAddressSDNode">; 314 315 def add : SDNode<"ISD::ADD" , SDTIntBinOp , 316 [SDNPCommutative, SDNPAssociative]>; 317 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>; 318 def mul : SDNode<"ISD::MUL" , SDTIntBinOp, 319 [SDNPCommutative, SDNPAssociative]>; 320 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>; 321 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>; 322 def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 323 def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>; 324 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>; 325 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>; 326 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>; 327 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>; 328 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>; 329 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>; 330 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>; 331 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>; 332 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>; 333 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>; 334 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>; 335 def and : SDNode<"ISD::AND" , SDTIntBinOp, 336 [SDNPCommutative, SDNPAssociative]>; 337 def or : SDNode<"ISD::OR" , SDTIntBinOp, 338 [SDNPCommutative, SDNPAssociative]>; 339 def xor : SDNode<"ISD::XOR" , SDTIntBinOp, 340 [SDNPCommutative, SDNPAssociative]>; 341 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp, 342 [SDNPCommutative, SDNPOutGlue]>; 343 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp, 344 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>; 345 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp, 346 [SDNPOutGlue]>; 347 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp, 348 [SDNPOutGlue, SDNPInGlue]>; 349 350 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>; 351 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>; 352 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>; 353 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>; 354 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>; 355 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>; 356 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>; 357 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>; 358 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>; 359 def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>; 360 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>; 361 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>; 362 363 364 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>; 365 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; 366 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; 367 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; 368 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; 369 def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>; 370 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; 371 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>; 372 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; 373 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; 374 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; 375 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>; 376 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>; 377 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>; 378 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>; 379 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>; 380 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>; 381 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>; 382 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>; 383 384 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>; 385 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>; 386 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>; 387 388 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>; 389 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>; 390 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>; 391 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>; 392 def f16_to_f32 : SDNode<"ISD::FP16_TO_FP32", SDTIntToFPOp>; 393 def f32_to_f16 : SDNode<"ISD::FP32_TO_FP16", SDTFPToIntOp>; 394 395 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>; 396 def select : SDNode<"ISD::SELECT" , SDTSelect>; 397 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>; 398 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>; 399 400 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>; 401 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>; 402 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>; 403 def trap : SDNode<"ISD::TRAP" , SDTNone, 404 [SDNPHasChain, SDNPSideEffect]>; 405 406 def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch, 407 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 408 SDNPMemOperand]>; 409 410 def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier, 411 [SDNPHasChain, SDNPSideEffect]>; 412 413 def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence, 414 [SDNPHasChain, SDNPSideEffect]>; 415 416 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3, 417 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 418 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2, 419 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 420 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2, 421 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 422 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2, 423 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 424 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2, 425 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 426 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2, 427 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 428 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2, 429 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 430 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2, 431 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 432 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2, 433 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 434 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2, 435 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 436 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2, 437 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 438 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2, 439 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 440 def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad, 441 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 442 def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore, 443 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 444 445 // Do not use ld, st directly. Use load, extload, sextload, zextload, store, 446 // and truncst (see below). 447 def ld : SDNode<"ISD::LOAD" , SDTLoad, 448 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 449 def st : SDNode<"ISD::STORE" , SDTStore, 450 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 451 def ist : SDNode<"ISD::STORE" , SDTIStore, 452 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 453 454 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; 455 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>; 456 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, 457 []>; 458 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT", 459 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>; 460 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT", 461 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>; 462 463 // This operator does not do subvector type checking. The ARM 464 // backend, at least, needs it. 465 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR", 466 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>, 467 []>; 468 469 // This operator does subvector type checking. 470 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>; 471 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>; 472 473 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use 474 // these internally. Don't reference these directly. 475 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID", 476 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>, 477 [SDNPHasChain]>; 478 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN", 479 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, 480 [SDNPHasChain]>; 481 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN", 482 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>; 483 484 // Do not use cvt directly. Use cvt forms below 485 def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>; 486 487 //===----------------------------------------------------------------------===// 488 // Selection DAG Condition Codes 489 490 class CondCode; // ISD::CondCode enums 491 def SETOEQ : CondCode; def SETOGT : CondCode; 492 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode; 493 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode; 494 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode; 495 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode; 496 497 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode; 498 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode; 499 500 501 //===----------------------------------------------------------------------===// 502 // Selection DAG Node Transformation Functions. 503 // 504 // This mechanism allows targets to manipulate nodes in the output DAG once a 505 // match has been formed. This is typically used to manipulate immediate 506 // values. 507 // 508 class SDNodeXForm<SDNode opc, code xformFunction> { 509 SDNode Opcode = opc; 510 code XFormFunction = xformFunction; 511 } 512 513 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>; 514 515 //===----------------------------------------------------------------------===// 516 // PatPred Subclasses. 517 // 518 // These allow specifying different sorts of predicates that control whether a 519 // node is matched. 520 // 521 class PatPred; 522 523 class CodePatPred<code predicate> : PatPred { 524 code PredicateCode = predicate; 525 } 526 527 528 //===----------------------------------------------------------------------===// 529 // Selection DAG Pattern Fragments. 530 // 531 // Pattern fragments are reusable chunks of dags that match specific things. 532 // They can take arguments and have C++ predicates that control whether they 533 // match. They are intended to make the patterns for common instructions more 534 // compact and readable. 535 // 536 537 /// PatFrag - Represents a pattern fragment. This can match something on the 538 /// DAG, from a single node to multiple nested other fragments. 539 /// 540 class PatFrag<dag ops, dag frag, code pred = [{}], 541 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator { 542 dag Operands = ops; 543 dag Fragment = frag; 544 code PredicateCode = pred; 545 code ImmediateCode = [{}]; 546 SDNodeXForm OperandTransform = xform; 547 } 548 549 // PatLeaf's are pattern fragments that have no operands. This is just a helper 550 // to define immediates and other common things concisely. 551 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm> 552 : PatFrag<(ops), frag, pred, xform>; 553 554 555 // ImmLeaf is a pattern fragment with a constraint on the immediate. The 556 // constraint is a function that is run on the immediate (always with the value 557 // sign extended out to an int64_t) as Imm. For example: 558 // 559 // def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>; 560 // 561 // this is a more convenient form to match 'imm' nodes in than PatLeaf and also 562 // is preferred over using PatLeaf because it allows the code generator to 563 // reason more about the constraint. 564 // 565 // If FastIsel should ignore all instructions that have an operand of this type, 566 // the FastIselShouldIgnore flag can be set. This is an optimization to reduce 567 // the code size of the generated fast instruction selector. 568 class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm> 569 : PatFrag<(ops), (vt imm), [{}], xform> { 570 let ImmediateCode = pred; 571 bit FastIselShouldIgnore = 0; 572 } 573 574 575 // Leaf fragments. 576 577 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>; 578 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>; 579 580 def immAllOnesV: PatLeaf<(build_vector), [{ 581 return ISD::isBuildVectorAllOnes(N); 582 }]>; 583 def immAllZerosV: PatLeaf<(build_vector), [{ 584 return ISD::isBuildVectorAllZeros(N); 585 }]>; 586 587 588 589 // Other helper fragments. 590 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>; 591 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>; 592 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>; 593 594 // load fragments. 595 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ 596 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 597 }]>; 598 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 599 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD; 600 }]>; 601 602 // extending load fragments. 603 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 604 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD; 605 }]>; 606 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 607 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD; 608 }]>; 609 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{ 610 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD; 611 }]>; 612 613 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 614 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 615 }]>; 616 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 617 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 618 }]>; 619 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 620 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 621 }]>; 622 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 623 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 624 }]>; 625 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 626 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32; 627 }]>; 628 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ 629 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64; 630 }]>; 631 632 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 633 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 634 }]>; 635 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 636 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 637 }]>; 638 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 639 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 640 }]>; 641 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ 642 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 643 }]>; 644 645 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 646 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1; 647 }]>; 648 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 649 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8; 650 }]>; 651 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 652 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16; 653 }]>; 654 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ 655 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32; 656 }]>; 657 658 // store fragments. 659 def unindexedstore : PatFrag<(ops node:$val, node:$ptr), 660 (st node:$val, node:$ptr), [{ 661 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED; 662 }]>; 663 def store : PatFrag<(ops node:$val, node:$ptr), 664 (unindexedstore node:$val, node:$ptr), [{ 665 return !cast<StoreSDNode>(N)->isTruncatingStore(); 666 }]>; 667 668 // truncstore fragments. 669 def truncstore : PatFrag<(ops node:$val, node:$ptr), 670 (unindexedstore node:$val, node:$ptr), [{ 671 return cast<StoreSDNode>(N)->isTruncatingStore(); 672 }]>; 673 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr), 674 (truncstore node:$val, node:$ptr), [{ 675 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 676 }]>; 677 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr), 678 (truncstore node:$val, node:$ptr), [{ 679 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 680 }]>; 681 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr), 682 (truncstore node:$val, node:$ptr), [{ 683 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 684 }]>; 685 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr), 686 (truncstore node:$val, node:$ptr), [{ 687 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 688 }]>; 689 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr), 690 (truncstore node:$val, node:$ptr), [{ 691 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64; 692 }]>; 693 694 // indexed store fragments. 695 def istore : PatFrag<(ops node:$val, node:$base, node:$offset), 696 (ist node:$val, node:$base, node:$offset), [{ 697 return !cast<StoreSDNode>(N)->isTruncatingStore(); 698 }]>; 699 700 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset), 701 (istore node:$val, node:$base, node:$offset), [{ 702 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 703 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 704 }]>; 705 706 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset), 707 (ist node:$val, node:$base, node:$offset), [{ 708 return cast<StoreSDNode>(N)->isTruncatingStore(); 709 }]>; 710 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 711 (itruncstore node:$val, node:$base, node:$offset), [{ 712 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 713 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC; 714 }]>; 715 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 716 (pre_truncst node:$val, node:$base, node:$offset), [{ 717 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 718 }]>; 719 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 720 (pre_truncst node:$val, node:$base, node:$offset), [{ 721 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 722 }]>; 723 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 724 (pre_truncst node:$val, node:$base, node:$offset), [{ 725 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 726 }]>; 727 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 728 (pre_truncst node:$val, node:$base, node:$offset), [{ 729 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 730 }]>; 731 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 732 (pre_truncst node:$val, node:$base, node:$offset), [{ 733 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 734 }]>; 735 736 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset), 737 (istore node:$val, node:$ptr, node:$offset), [{ 738 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 739 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 740 }]>; 741 742 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset), 743 (itruncstore node:$val, node:$base, node:$offset), [{ 744 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode(); 745 return AM == ISD::POST_INC || AM == ISD::POST_DEC; 746 }]>; 747 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset), 748 (post_truncst node:$val, node:$base, node:$offset), [{ 749 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1; 750 }]>; 751 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset), 752 (post_truncst node:$val, node:$base, node:$offset), [{ 753 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8; 754 }]>; 755 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset), 756 (post_truncst node:$val, node:$base, node:$offset), [{ 757 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; 758 }]>; 759 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset), 760 (post_truncst node:$val, node:$base, node:$offset), [{ 761 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32; 762 }]>; 763 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset), 764 (post_truncst node:$val, node:$base, node:$offset), [{ 765 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32; 766 }]>; 767 768 // setcc convenience fragments. 769 def setoeq : PatFrag<(ops node:$lhs, node:$rhs), 770 (setcc node:$lhs, node:$rhs, SETOEQ)>; 771 def setogt : PatFrag<(ops node:$lhs, node:$rhs), 772 (setcc node:$lhs, node:$rhs, SETOGT)>; 773 def setoge : PatFrag<(ops node:$lhs, node:$rhs), 774 (setcc node:$lhs, node:$rhs, SETOGE)>; 775 def setolt : PatFrag<(ops node:$lhs, node:$rhs), 776 (setcc node:$lhs, node:$rhs, SETOLT)>; 777 def setole : PatFrag<(ops node:$lhs, node:$rhs), 778 (setcc node:$lhs, node:$rhs, SETOLE)>; 779 def setone : PatFrag<(ops node:$lhs, node:$rhs), 780 (setcc node:$lhs, node:$rhs, SETONE)>; 781 def seto : PatFrag<(ops node:$lhs, node:$rhs), 782 (setcc node:$lhs, node:$rhs, SETO)>; 783 def setuo : PatFrag<(ops node:$lhs, node:$rhs), 784 (setcc node:$lhs, node:$rhs, SETUO)>; 785 def setueq : PatFrag<(ops node:$lhs, node:$rhs), 786 (setcc node:$lhs, node:$rhs, SETUEQ)>; 787 def setugt : PatFrag<(ops node:$lhs, node:$rhs), 788 (setcc node:$lhs, node:$rhs, SETUGT)>; 789 def setuge : PatFrag<(ops node:$lhs, node:$rhs), 790 (setcc node:$lhs, node:$rhs, SETUGE)>; 791 def setult : PatFrag<(ops node:$lhs, node:$rhs), 792 (setcc node:$lhs, node:$rhs, SETULT)>; 793 def setule : PatFrag<(ops node:$lhs, node:$rhs), 794 (setcc node:$lhs, node:$rhs, SETULE)>; 795 def setune : PatFrag<(ops node:$lhs, node:$rhs), 796 (setcc node:$lhs, node:$rhs, SETUNE)>; 797 def seteq : PatFrag<(ops node:$lhs, node:$rhs), 798 (setcc node:$lhs, node:$rhs, SETEQ)>; 799 def setgt : PatFrag<(ops node:$lhs, node:$rhs), 800 (setcc node:$lhs, node:$rhs, SETGT)>; 801 def setge : PatFrag<(ops node:$lhs, node:$rhs), 802 (setcc node:$lhs, node:$rhs, SETGE)>; 803 def setlt : PatFrag<(ops node:$lhs, node:$rhs), 804 (setcc node:$lhs, node:$rhs, SETLT)>; 805 def setle : PatFrag<(ops node:$lhs, node:$rhs), 806 (setcc node:$lhs, node:$rhs, SETLE)>; 807 def setne : PatFrag<(ops node:$lhs, node:$rhs), 808 (setcc node:$lhs, node:$rhs, SETNE)>; 809 810 def atomic_cmp_swap_8 : 811 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 812 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 813 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 814 }]>; 815 def atomic_cmp_swap_16 : 816 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 817 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 818 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 819 }]>; 820 def atomic_cmp_swap_32 : 821 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 822 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 823 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 824 }]>; 825 def atomic_cmp_swap_64 : 826 PatFrag<(ops node:$ptr, node:$cmp, node:$swap), 827 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{ 828 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 829 }]>; 830 831 multiclass binary_atomic_op<SDNode atomic_op> { 832 def _8 : PatFrag<(ops node:$ptr, node:$val), 833 (atomic_op node:$ptr, node:$val), [{ 834 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 835 }]>; 836 def _16 : PatFrag<(ops node:$ptr, node:$val), 837 (atomic_op node:$ptr, node:$val), [{ 838 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 839 }]>; 840 def _32 : PatFrag<(ops node:$ptr, node:$val), 841 (atomic_op node:$ptr, node:$val), [{ 842 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 843 }]>; 844 def _64 : PatFrag<(ops node:$ptr, node:$val), 845 (atomic_op node:$ptr, node:$val), [{ 846 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 847 }]>; 848 } 849 850 defm atomic_load_add : binary_atomic_op<atomic_load_add>; 851 defm atomic_swap : binary_atomic_op<atomic_swap>; 852 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>; 853 defm atomic_load_and : binary_atomic_op<atomic_load_and>; 854 defm atomic_load_or : binary_atomic_op<atomic_load_or>; 855 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>; 856 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>; 857 defm atomic_load_min : binary_atomic_op<atomic_load_min>; 858 defm atomic_load_max : binary_atomic_op<atomic_load_max>; 859 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>; 860 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>; 861 defm atomic_store : binary_atomic_op<atomic_store>; 862 863 def atomic_load_8 : 864 PatFrag<(ops node:$ptr), 865 (atomic_load node:$ptr), [{ 866 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8; 867 }]>; 868 def atomic_load_16 : 869 PatFrag<(ops node:$ptr), 870 (atomic_load node:$ptr), [{ 871 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16; 872 }]>; 873 def atomic_load_32 : 874 PatFrag<(ops node:$ptr), 875 (atomic_load node:$ptr), [{ 876 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32; 877 }]>; 878 def atomic_load_64 : 879 PatFrag<(ops node:$ptr), 880 (atomic_load node:$ptr), [{ 881 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64; 882 }]>; 883 884 //===----------------------------------------------------------------------===// 885 // Selection DAG CONVERT_RNDSAT patterns 886 887 def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 888 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 889 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF; 890 }]>; 891 892 def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 893 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 894 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS; 895 }]>; 896 897 def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 898 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 899 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU; 900 }]>; 901 902 def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 903 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 904 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US; 905 }]>; 906 907 def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 908 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 909 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU; 910 }]>; 911 912 def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 913 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 914 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF; 915 }]>; 916 917 def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 918 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 919 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF; 920 }]>; 921 922 def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 923 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 924 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS; 925 }]>; 926 927 def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat), 928 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{ 929 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU; 930 }]>; 931 932 //===----------------------------------------------------------------------===// 933 // Selection DAG Pattern Support. 934 // 935 // Patterns are what are actually matched against by the target-flavored 936 // instruction selection DAG. Instructions defined by the target implicitly 937 // define patterns in most cases, but patterns can also be explicitly added when 938 // an operation is defined by a sequence of instructions (e.g. loading a large 939 // immediate value on RISC targets that do not support immediates as large as 940 // their GPRs). 941 // 942 943 class Pattern<dag patternToMatch, list<dag> resultInstrs> { 944 dag PatternToMatch = patternToMatch; 945 list<dag> ResultInstrs = resultInstrs; 946 list<Predicate> Predicates = []; // See class Instruction in Target.td. 947 int AddedComplexity = 0; // See class Instruction in Target.td. 948 } 949 950 // Pat - A simple (but common) form of a pattern, which produces a simple result 951 // not needing a full list. 952 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>; 953 954 //===----------------------------------------------------------------------===// 955 // Complex pattern definitions. 956 // 957 958 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code 959 // in C++. NumOperands is the number of operands returned by the select function; 960 // SelectFunc is the name of the function used to pattern match the max. pattern; 961 // RootNodes are the list of possible root nodes of the sub-dags to match. 962 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>; 963 // 964 class ComplexPattern<ValueType ty, int numops, string fn, 965 list<SDNode> roots = [], list<SDNodeProperty> props = []> { 966 ValueType Ty = ty; 967 int NumOperands = numops; 968 string SelectFunc = fn; 969 list<SDNode> RootNodes = roots; 970 list<SDNodeProperty> Properties = props; 971 } 972
