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/external/vulkan-validation-layers/tests/gtest-1.7.0/m4/
acx_pthread.m4	240 # architectures and systems. The problem is that in certain 256 # FIXME: -fPIC is required for -shared on many architectures, 297 # Linux gcc on some architectures such as mips/mipsel forgets
/prebuilts/go/darwin-x86/doc/
install.html	22 architectures. 36 Go binary distributions are available for these supported operating systems and architectures. 46 <th align="center">Architectures</th>
/prebuilts/go/linux-x86/doc/
install.html	22 architectures. 36 Go binary distributions are available for these supported operating systems and architectures. 46 <th align="center">Architectures</th>
/toolchain/binutils/binutils-2.25/gas/doc/
c-i960.texi	46 960 (even if this means mixing architectures!). In principle, 59 architectures.) If @var{BR} represents a conditional branch instruction, 231 The 960 architectures provide combined Compare-and-Branch instructions
/toolchain/binutils/binutils-2.25/opcodes/
cgen-ibld.in	144 /* For architectures with insns smaller than the base-insn-bitsize, 302 /* For architectures with insns smaller than the base-insn-bitsize, 449 /* For architectures with insns smaller than the insn-base-bitsize,
/external/llvm/docs/
Atomics.rst	268 Architectures with weak memory ordering (essentially everything relevant today 271 a simple implementation, most architectures provide a barrier which is strong 408 On architectures which use barrier instructions for all atomic ordering (like 426 load`` must *also* expand to a library call on such architectures, so that it 443 On ARM (before v8), MIPS, and many other RISC architectures, Acquire, Release, 600 architectures support atomic loads and stores directly (possibly by emitting a
CompilerWriterInfo.rst	37 * `MIPS Processor Architecture <http://imgtec.com/mips/mips-architectures.asp>`_ 94 * `Intel 64 and IA-32 manuals <http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html>`_
/external/swiftshader/third_party/LLVM/docs/
Atomics.html	341 <dd>Architectures with weak memory ordering (essentially everything relevant 344 architecture, but for a simple implementation, most architectures provide 509 <code>ATOMIC_*</code> opcodes. On architectures which use barrier 518 <p>Common architectures have some way of representing at least a pointer-sized 527 <p>The implementation of atomics on LL/SC architectures (like ARM) is currently 545 <p>On ARM, MIPS, and many other RISC architectures, Acquire, Release, and
DebuggingJITedCode.html	110 different ways. For example, on most 32-bit x86 architectures, you can simply 133 <p>At the time of this writing, LLVM only supports architectures that use ELF
/art/test/137-cfi/
cfi.cc	48 // On supported architectures we cause a real SEGV. 51 // On other architectures we simulate SEGV.
/bionic/libc/kernel/tools/
kernel.py	201 'archs' is a list of architectures 272 """scan for all architectures and return the set of all needed kernel headers"""
/cts/common/host-side/tradefed/tests/src/com/android/compatibility/common/tradefed/testtype/
CompatibilityTestTest.java	67 * supported architectures and Device supported architectures.
/device/linaro/bootloader/edk2/
BuildNotes2.txt	49 and X64 target architectures and DDK3790 for IPF target architectures. To use a
/docs/source.android.com/en/source/
64-bit-builds.html	29 supports building binaries for two target CPU architectures (64-bit and 32-bit) 33 rules to build binaries for both architectures. The product configuration
/external/clang/tools/scan-build-py/libscanbuild/
runner.py	251 """ Do run analyzer through one of the given architectures. """ 257 # filter out disabled architectures and -arch switches
/external/compiler-rt/lib/safestack/
safestack.cc	34 // architectures: the (safe) stack segment (implicitly accessed via the %ss 46 // 3) Protection via information hiding on 64 bit architectures: the location
/external/freetype/src/base/
md5.c	48 * architectures that lack an AND-NOT instruction, just like in Colin Plumb's 69 * The check for little-endian architectures that tolerate unaligned memory
/external/gemmlowp/doc/
kernel.md	8 gemmlowp is designed to be easily extensible to different architectures and 27 Thus, in order to allow efficient specialization to diverse architectures,
kernels.txt	11 gemmlowp is designed to be easily extensible to different architectures and 31 Thus, in order to allow efficient specialization to diverse architectures,
packing.md	143 for particular CPU architectures. To allow that, we handle at a time blocks of 190 ## Specialized packing paths for specific formats on specific CPU architectures
/external/libvorbis/doc/
02-bitpacking.tex	21 In most contemporary architectures, a 'byte' is synonymous with an 32 The most ubiquitous architectures today consider a 'byte' to be an
/external/libvpx/libvpx/build/make/
iosbuild.sh	160 # Architectures in the fat file: $FRAMEWORK_LIB <architectures>
/external/llvm/docs/CommandGuide/
lli.rst	16 :program:`lli` is *not* an emulator. It will not execute IR of different architectures 76 valid architectures. By default this is inferred from the target triple or
/external/pdfium/third_party/freetype/src/base/
md5.c	48 * architectures that lack an AND-NOT instruction, just like in Colin Plumb's 69 * The check for little-endian architectures that tolerate unaligned
/external/tcpdump/
extract.h	53 * We do this only for specific architectures because, for example, 57 * XXX - add other architectures and compilers as possible and

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