| /prebuilts/go/linux-x86/src/cmd/internal/obj/mips/ |
| asm0.go | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 755 CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero));
[all...] |
| MipsSEFrameLowering.cpp | 272 // The case where dmtc1 is available doesn't need to be handled here
[all...] |
| /external/llvm/test/MC/Disassembler/Mips/micromips64r6/ |
| valid.txt | 204 0x56 0x74 0x2c 0x3b # CHECK: dmtc1 $19, $f20
|
| /external/llvm/test/MC/Disassembler/Mips/mips4/ |
| valid-mips4.txt | 148 0x44 0xb0 0x70 0x00 # CHECK: dmtc1 $16, $f14
|
| /external/llvm/test/MC/Mips/mips4/ |
| valid.s | 81 dmtc1 $s0,$f14
|
| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 81 dmtc1 $s0,$f14
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 88 dmtc1 $s0,$f14
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 90 dmtc1 $s0,$f14
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 90 dmtc1 $s0,$f14
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 90 dmtc1 $s0,$f14
|
| /external/llvm/test/MC/Mips/ |
| target-soft-float.s | 13 dmtc1 $6, $f2
|
| /art/compiler/optimizing/ |
| intrinsics_mips64.cc | 192 __ Dmtc1(in, out);
867 __ Dmtc1(AT, out);
[all...] |
| code_generator_mips64.cc | [all...] |
| /external/v8/src/compiler/mips64/ |
| code-generator-mips64.cc | [all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64_test.cc | 647 TEST_F(AssemblerMIPS64Test, Dmtc1) {
648 DriverStr(RepeatRF(&mips64::Mips64Assembler::Dmtc1, "dmtc1 ${reg1}, ${reg2}"), "Dmtc1");
[all...] |
| assembler_mips64.h | 642 void Dmtc1(GpuRegister rt, FpuRegister fs); // MIPS64
[all...] |
| assembler_mips64.cc | [all...] |
| /art/disassembler/ |
| disassembler_mips.cc | 376 { kFpMask | (0x1f << 21), kCop1 | (0x05 << 21), "dmtc1", "Td" },
[all...] |
| /external/v8/src/mips64/ |
| constants-mips64.h | 529 DMTC1 = ((0U << 3) + 5) << 21,
[all...] |
| assembler-mips64.cc | 2651 void Assembler::dmtc1(Register rt, FPURegister fs) { function in class:v8::internal::Assembler
[all...] |
| assembler-mips64.h | [all...] |
| macro-assembler-mips64.h | 317 inline void Move(FPURegister dst, Register src) { dmtc1(src, dst); }
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| ChangeLog | 340 (dmtc1, mtc1, mthc1): Add COD attribute.
|
| micromips-opc.c | [all...] |
