| /external/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 202 unsigned SrcReg = getCompareSourceReg(Compare);
205 if (getRegReferences(*MBBI, SrcReg))
340 unsigned SrcReg = getCompareSourceReg(Compare);
348 if (resultTests(MI, SrcReg)) {
363 SrcRefs |= getRegReferences(MI, SrcReg);
406 unsigned SrcReg = Compare.getOperand(0).getReg();
411 if (MBBI->modifiesRegister(SrcReg, TRI) ||
455 // Clear any intervening kills of SrcReg and SrcReg2.
458 MBBI->clearRegisterKills(SrcReg, TRI);
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| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyInstrInfo.h | 41 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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| WebAssemblyInstrInfo.cpp | 54 unsigned SrcReg, bool KillSrc) const {
76 .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| r500_fragprog_emit.c | 415 use_temporary(code, inst->SrcReg[0].Index);
419 code->inst[ip].inst2 = R500_TEX_SRC_ADDR(inst->SrcReg[0].Index)
420 | (translate_strq_swizzle(inst->SrcReg[0].Swizzle) << 8)
429 use_temporary(code, inst->SrcReg[1].Index);
430 use_temporary(code, inst->SrcReg[2].Index);
434 R500_DX_ADDR(inst->SrcReg[1].Index) |
435 (translate_strq_swizzle(inst->SrcReg[1].Swizzle) << 8) |
436 R500_DY_ADDR(inst->SrcReg[2].Index) |
437 (translate_strq_swizzle(inst->SrcReg[2].Swizzle) << 24);
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| radeon_compiler_util.h | 73 struct rc_src_register lmul_swizzle(unsigned int swizzle, struct rc_src_register srcreg);
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| r3xx_fragprog.c | 76 inst->SrcReg[i] = lmul_swizzle(RC_SWIZZLE_ZZZZ, inst->SrcReg[i]);
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| radeon_program.h | 66 struct rc_src_register SrcReg[2];
78 struct rc_src_register SrcReg[3];
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| /external/mesa3d/src/gallium/drivers/r300/compiler/tests/ |
| radeon_compiler_regalloc_tests.c | 72 if (GET_SWZ(inst->U.I.SrcReg[0].Swizzle, 0)
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| /external/mesa3d/src/mesa/main/ |
| atifragshader.c | 673 curI->SrcReg[optype][0].Index = arg1;
674 curI->SrcReg[optype][0].argRep = arg1Rep;
675 curI->SrcReg[optype][0].argMod = arg1Mod;
679 curI->SrcReg[optype][1].Index = arg2;
680 curI->SrcReg[optype][1].argRep = arg2Rep;
681 curI->SrcReg[optype][1].argMod = arg2Mod;
685 curI->SrcReg[optype][2].Index = arg3;
686 curI->SrcReg[optype][2].argRep = arg3Rep;
687 curI->SrcReg[optype][2].argMod = arg3Mod;
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| atifragshader.h | 52 struct atifragshader_src_register SrcReg[2][3];
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| /external/mesa3d/src/mesa/state_tracker/ |
| st_atifs_to_tgsi.c | 152 const struct atifragshader_src_register *srcReg)
154 struct ureg_src src = get_source(t, srcReg->Index);
157 switch (srcReg->argRep) {
175 if (srcReg->argMod & GL_COMP_BIT_ATI) {
182 if (srcReg->argMod & GL_BIAS_BIT_ATI) {
189 if (srcReg->argMod & GL_2X_BIT_ATI) {
196 if (srcReg->argMod & GL_NEGATE_BIT_ATI) {
373 &inst->SrcReg[optype][arg]);
584 GLint index = inst->SrcReg[optype][arg].Index;
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 109 unsigned DestReg, unsigned SrcReg,
112 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
113 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
116 .addReg(SrcReg, getKillRegState(KillSrc)));
121 unsigned SrcReg, bool isKill, int FI,
139 .addReg(SrcReg, getKillRegState(isKill))
144 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
579 unsigned SrcReg = SrcMI->getOperand(1).getReg();
591 NMI->modifiesRegister(SrcReg, &TRI) ||
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| ARMBaseInstrInfo.h | 111 unsigned DestReg, unsigned SrcReg,
116 unsigned SrcReg, bool isKill, int FrameIndex,
188 /// in SrcReg and the value it compares against in CmpValue. Return true if
190 virtual bool AnalyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
195 virtual bool OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
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| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreRegisterInfo.h | 36 unsigned SrcReg, int Offset, DebugLoc dl) const;
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| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 492 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>
505 unsigned SrcReg = MI.getOperand(0).getReg();
508 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg.
510 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
514 if (SrcReg != PPC::CR0) {
521 .addImm(getEncodingValue(SrcReg) * 4)
580 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset>
593 unsigned SrcReg = MI.getOperand(0).getReg();
596 getCRFromCRBit(SrcReg))
597 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()))
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmInstrumentation.cpp | 225 void InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg, unsigned CntReg,
292 void X86AddressSanitizer::InstrumentMOVSBase(unsigned DstReg, unsigned SrcReg,
297 // and [SrcReg .. SrcReg + AccessSize * (CntReg - 1)].
303 RegCtx.AddBusyReg(SrcReg);
308 // Test (%SrcReg)
312 getPointerWidth(), 0, Disp, SrcReg, 0, AccessSize, SMLoc(), SMLoc()));
317 // Test -1(%SrcReg, %CntReg, AccessSize)
321 getPointerWidth(), 0, Disp, SrcReg, CntReg, AccessSize, SMLoc(),
745 InstrumentMOVSBase(X86::EDI /* DstReg */, X86::ESI /* SrcReg */,
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineCSE.cpp | 135 unsigned SrcReg = DefMI->getOperand(1).getReg();
136 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
144 // RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
146 // MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
155 if (!MRI->constrainRegClass(SrcReg, RC))
159 // Propagate SrcReg of copies to MI.
160 MO.setReg(SrcReg);
161 MRI->clearKillFlags(SrcReg);
|
| TailDuplicator.cpp | 172 unsigned SrcReg = LI->second[j].second;
173 SSAUpdate.AddAvailableValue(SrcBB, SrcReg);
280 unsigned SrcReg = MI.getOperand(i).getReg();
281 UsedByPhi->insert(SrcReg);
311 unsigned SrcReg = MI->getOperand(SrcOpIdx).getReg();
314 LocalVRMap.insert(std::make_pair(DefReg, RegSubRegPair(SrcReg, SrcSubReg)));
319 Copies.push_back(std::make_pair(NewDef, RegSubRegPair(SrcReg, SrcSubReg)));
475 unsigned SrcReg = LI->second[j].second;
477 II->getOperand(Idx).setReg(SrcReg);
481 MIB.addReg(SrcReg).addMBB(SrcBB)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.h | 47 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
52 unsigned SrcReg, bool isKill, int FrameIndex,
|
| MipsSEInstrInfo.h | 47 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
52 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| intel_tiled_memcpy.c | 124 __m128i srcreg, dstreg, agmask, ag, rb, br; local
127 srcreg = _mm_loadu_si128((__m128i *)src);
129 rb = _mm_andnot_si128(agmask, srcreg);
130 ag = _mm_and_si128(agmask, srcreg);
141 __m128i srcreg, dstreg, agmask, ag, rb, br; local
144 srcreg = _mm_load_si128((__m128i *)src);
146 rb = _mm_andnot_si128(agmask, srcreg);
147 ag = _mm_and_si128(agmask, srcreg);
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsExpandPseudo.cpp | 104 unsigned SrcReg = I->getOperand(1).getReg();
108 const unsigned* SubReg = TM.getRegisterInfo()->getSubRegisters(SrcReg);
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZInstrInfo.h | 67 unsigned DestReg, unsigned SrcReg,
75 unsigned SrcReg, bool isKill,
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCCompound.cpp | 84 unsigned DstReg, SrcReg, Src1Reg, Src2Reg;
115 SrcReg = MI.getOperand(1).getReg();
117 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
127 SrcReg = MI.getOperand(1).getReg();
129 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg))
|
| /external/libvpx/libvpx/vpx_dsp/x86/ |
| vpx_subpixel_8t_intrin_ssse3.c | 56 __m128i addFilterReg64, filtersReg, srcReg, minReg;
82 srcReg = _mm_loadu_si128((const __m128i *)(src_ptr - 3));
85 srcRegFilt1 = _mm_shuffle_epi8(srcReg, shuffle1);
86 srcRegFilt2 = _mm_shuffle_epi8(srcReg, shuffle2);
122 __m128i firstFilters, secondFilters, thirdFilters, forthFilters, srcReg;
154 srcReg = _mm_loadu_si128((const __m128i *)(src_ptr - 3));
157 srcRegFilt1 = _mm_shuffle_epi8(srcReg, filt1Reg);
158 srcRegFilt2 = _mm_shuffle_epi8(srcReg, filt2Reg);
165 srcRegFilt3 = _mm_shuffle_epi8(srcReg, filt3Reg);
166 srcRegFilt4 = _mm_shuffle_epi8(srcReg, filt4Reg)
[all...] |
