| /external/llvm/lib/CodeGen/ |
| MachineSink.cpp | 163 unsigned SrcReg = MI.getOperand(1).getReg();
165 if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
167 !MRI->hasOneNonDBGUse(SrcReg))
170 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
175 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
180 MRI->replaceRegWith(DstReg, SrcReg);
185 MRI->clearKillFlags(SrcReg);
|
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMExpandPseudoInsts.cpp | 495 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
497 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
509 MIB->addRegisterKilled(SrcReg, TRI, true);
621 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
623 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
638 MIB->addRegisterKilled(SrcReg, TRI, true);
[all...] |
| ARMAsmPrinter.cpp | [all...] |
| Thumb2ITBlockPass.cpp | 121 unsigned SrcReg = MI->getOperand(1).getReg();
124 if (Uses.count(DstReg) || Defs.count(SrcReg))
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| MachineCSE.cpp | 130 unsigned SrcReg = DefMI->getOperand(1).getReg();
131 if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
135 if (!MRI->constrainRegClass(SrcReg, MRI->getRegClass(Reg)))
139 MO.setReg(SrcReg);
140 MRI->clearKillFlags(SrcReg);
|
| StackSlotColoring.cpp | 633 } else if (unsigned SrcReg = TII->isStoreToStackSlot(MI, OldFI)) {
634 if (MI->killsRegister(SrcReg) && PropagateBackward(MI, MBB, SrcReg, Reg)) {
640 .addReg(SrcReg);
|
| VirtRegRewriter.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 158 unsigned SrcReg = DefMI->getOperand(i).getReg();
159 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
160 DefMI = MRI->getVRegDef(SrcReg);
|
| Thumb2ITBlockPass.cpp | 138 unsigned SrcReg = MI->getOperand(1).getReg();
141 if (Uses.count(DstReg) || Defs.count(SrcReg))
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 183 bool loadImmediate(int64_t ImmValue, unsigned DstReg, unsigned SrcReg,
188 unsigned SrcReg, bool Is32BitSym, SMLoc IDLoc,
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| r300_fragprog_emit.c | 455 use_temporary(code, inst->U.I.SrcReg[0].Index);
458 ((inst->U.I.SrcReg[0].Index << R300_SRC_ADDR_SHIFT)
464 | (inst->U.I.SrcReg[0].Index >= R300_PFS_NUM_TEMP_REGS ?
|
| radeon_compiler_util.c | 288 struct rc_src_register lmul_swizzle(unsigned int swizzle, struct rc_src_register srcreg)
290 struct rc_src_register tmp = srcreg;
297 tmp.Swizzle |= GET_SWZ(srcreg.Swizzle, swz) << (i*3);
298 tmp.Negate |= GET_BIT(srcreg.Negate, swz) << i;
|
| radeon_inline_literals.c | 112 &inst->U.I.SrcReg[src_idx];
|
| /external/mesa3d/src/mesa/swrast/ |
| s_atifragshader.c | 335 GLint index = inst->SrcReg[optype][i].Index;
360 apply_src_rep(optype, inst->SrcReg[optype][i].argRep,
362 apply_src_mod(optype, inst->SrcReg[optype][i].argMod,
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| TargetInstrInfo.h | 110 unsigned &SrcReg, unsigned &DstReg,
359 unsigned DestReg, unsigned SrcReg,
371 unsigned SrcReg, bool isKill, int FrameIndex,
602 /// in SrcReg and the value it compares against in CmpValue. Return true if
605 unsigned &SrcReg, int &Mask, int &Value) const {
613 unsigned SrcReg, int Mask, int Value,
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 458 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset>, <FI>
467 unsigned SrcReg = MI.getOperand(0).getReg();
471 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg.
473 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
477 if (SrcReg != PPC::CR0)
481 .addImm(getPPCRegisterNumbering(SrcReg) * 4)
|
| /external/llvm/lib/Target/AMDGPU/ |
| R600InstrInfo.h | 66 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
284 unsigned DstReg, unsigned SrcReg) const;
|
| R600InstrInfo.cpp | 45 unsigned SrcReg, bool KillSrc) const {
49 (AMDGPU::R600_Reg128RegClass.contains(SrcReg) ||
50 AMDGPU::R600_Reg128VerticalRegClass.contains(SrcReg))) {
54 (AMDGPU::R600_Reg64RegClass.contains(SrcReg) ||
55 AMDGPU::R600_Reg64VerticalRegClass.contains(SrcReg))) {
64 RI.getSubReg(SrcReg, SubRegIndex))
70 DestReg, SrcReg);
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFrameLowering.cpp | 80 static void writeSPToMemory(unsigned SrcReg, MachineFunction &MF,
103 .addReg(SrcReg)
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 64 unsigned SrcReg = MI.getOperand(OpNum).getReg();
66 if ((SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15) ||
67 (SrcReg >= X86::YMM8 && SrcReg <= X86::YMM15))
490 unsigned SrcReg = MI.getOperand(i).getReg();
491 if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.h | 43 unsigned SrcReg,
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.h | 161 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
170 unsigned SrcReg, bool isKill, int FrameIndex,
247 /// in SrcReg and SrcReg2 if having two register operands, and the value it
250 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
|
| /external/mesa3d/src/mesa/program/ |
| program_parser.h | 127 struct asm_src_register SrcReg[3];
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.h | 43 unsigned SrcReg,
|
