| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| PTXInstrInfo.h | 42 unsigned DstReg, unsigned SrcReg,
47 unsigned DstReg, unsigned SrcReg,
53 unsigned &SrcReg, unsigned &DstReg,
104 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 135 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
137 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
139 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
140 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
143 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
145 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
146 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
148 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
169 MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
171 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCQPXLoadSplat.cpp | 88 unsigned SrcReg = SMI->getOperand(1).getReg();
90 if (MI->modifiesRegister(SrcReg, TRI)) {
105 if (SplatReg != SrcReg) {
109 TRI->getSubRegIndex(SrcReg, MI->getOperand(0).getReg());
115 MI->substituteRegister(SrcReg, SplatReg, 0, *TRI);
140 (SrcReg != SplatReg &&
|
| PPCMIPeephole.cpp | 59 // Find the "true" register represented by SrcReg (following chains
61 unsigned lookThruCopyLike(unsigned SrcReg);
195 // the original SrcReg unless it is the target of a copy-like
199 unsigned PPCMIPeephole::lookThruCopyLike(unsigned SrcReg) {
203 MachineInstr *MI = MRI->getVRegDef(SrcReg);
205 return SrcReg;
218 SrcReg = CopySrcReg;
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 305 unsigned SrcReg, bool KillSrc) const {
318 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
320 .addReg(SrcReg, getKillRegState(KillSrc));
321 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) {
326 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
328 .addReg(SrcReg, getKillRegState(KillSrc));
329 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
332 .addReg(SrcReg, getKillRegState(KillSrc));
339 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) {
343 .addReg(SrcReg, getKillRegState(KillSrc))
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| StrongPHIElimination.cpp | 250 unsigned SrcReg = SrcMO.getReg();
251 addReg(SrcReg);
252 unionRegs(DestReg, SrcReg);
254 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
292 unsigned SrcReg = BBI->getOperand(i).getReg();
293 addReg(SrcReg);
294 unionRegs(DestReg, SrcReg);
309 unsigned SrcReg = PHI->getOperand(1).getReg();
310 unsigned SrcColor = getRegColor(SrcReg);
313 NewReg = SrcReg;
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.h | 46 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
119 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
123 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
127 MachineBasicBlock::iterator MBBI, unsigned SrcReg,
163 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
165 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
170 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
211 bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
215 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
220 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
[all...] |
| AArch64InstrInfo.cpp | 445 unsigned SrcReg = Cond[2].getReg();
448 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass);
450 .addReg(SrcReg)
454 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass);
456 .addReg(SrcReg)
638 unsigned &SrcReg, unsigned &DstReg,
650 SrcReg = MI.getOperand(1).getReg();
690 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
692 bool AArch64InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
711 SrcReg = MI.getOperand(1).getReg()
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_dataflow_deadcode.c | 43 unsigned char SrcReg[3];
186 unsigned int newsrcmask = srcmasks[src] & ~insts->SrcReg[src];
187 insts->SrcReg[src] |= newsrcmask;
191 refmask |= 1 << GET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan);
200 mark_used(s, inst->U.I.SrcReg[src].File, inst->U.I.SrcReg[src].Index, refmask);
202 if (inst->U.I.SrcReg[src].RelAddr)
260 ptr->U.I.SrcReg[src].File,
261 ptr->U.I.SrcReg[src].Index,
353 SET_SWZ(inst->U.I.SrcReg[src].Swizzle, chan, RC_SWIZZLE_UNUSED)
[all...] |
| r500_fragprog.c | 56 var_list, inst_if->Type, &inst_if->U.I.SrcReg[0]);
99 if (GET_SWZ(inst_if->U.I.SrcReg[0].Swizzle, 0) == RC_SWIZZLE_X) {
113 inst_mov->U.I.SrcReg[0] = inst_if->U.I.SrcReg[0];
115 inst_mov->U.I.SrcReg[0].Swizzle = combine_swizzles4(
116 inst_mov->U.I.SrcReg[0].Swizzle,
120 inst_mov->U.I.SrcReg[0].Swizzle = combine_swizzles4(
121 inst_mov->U.I.SrcReg[0].Swizzle,
165 temp_src = writer->Inst->U.I.SrcReg[0];
166 writer->Inst->U.I.SrcReg[0]
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 104 unsigned DestReg, unsigned SrcReg,
109 if (Mips::CPURegsRegClass.contains(SrcReg))
111 else if (Mips::CCRRegClass.contains(SrcReg))
113 else if (Mips::FGR32RegClass.contains(SrcReg))
115 else if (SrcReg == Mips::HI)
116 Opc = Mips::MFHI, SrcReg = 0;
117 else if (SrcReg == Mips::LO)
118 Opc = Mips::MFLO, SrcReg = 0;
120 else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
130 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCDuplexInfo.cpp | 178 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg;
190 SrcReg = MCI.getOperand(1).getReg();
194 if (HexagonMCInstrInfo::isIntReg(SrcReg) &&
195 Hexagon::R29 == SrcReg && inRange<5, 2>(MCI, 2)) {
199 if (HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
208 SrcReg = MCI.getOperand(1).getReg();
210 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
229 SrcReg = MCI.getOperand(1).getReg();
231 HexagonMCInstrInfo::isIntRegForSubInst(SrcReg) &&
239 SrcReg = MCI.getOperand(1).getReg()
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrFormats.td | 30 def SrcReg : SourceMode<0>;
98 : IForm8<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
110 : IForm8<opcode, DstMem, SrcReg, Size4Bytes, outs, ins, asmstr, pattern>;
127 : IForm16<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
139 : IForm16<opcode, DstMem, SrcReg, Size4Bytes, outs, ins, asmstr, pattern>;
169 : IIForm8<opcode, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
186 : IIForm16<opcode, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
|
| MSP430InstrInfo.cpp | 39 unsigned SrcReg, bool isKill, int FrameIdx,
55 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
59 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
94 unsigned SrcReg, bool KillSrc) const {
96 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
98 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
104 .addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430InstrFormats.td | 30 def SrcReg : SourceMode<0>;
98 : IForm8<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
110 : IForm8<opcode, DstMem, SrcReg, Size4Bytes, outs, ins, asmstr, pattern>;
127 : IForm16<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
139 : IForm16<opcode, DstMem, SrcReg, Size4Bytes, outs, ins, asmstr, pattern>;
169 : IIForm8<opcode, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
186 : IIForm16<opcode, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
|
| MSP430InstrInfo.cpp | 37 unsigned SrcReg, bool isKill, int FrameIdx,
55 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
59 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
93 unsigned DestReg, unsigned SrcReg,
96 if (MSP430::GR16RegClass.contains(DestReg, SrcReg))
98 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg))
104 .addReg(SrcReg, getKillRegState(KillSrc));
|
| /external/mesa3d/src/mesa/program/ |
| prog_print.c | 535 const struct prog_src_register *srcReg,
540 reg_string((gl_register_file) srcReg->File,
541 srcReg->Index, mode, srcReg->RelAddr, prog),
542 _mesa_swizzle_string(srcReg->Swizzle,
543 srcReg->Negate, GL_FALSE));
546 _mesa_register_file_name((gl_register_file) srcReg->File),
547 srcReg->Index,
548 _mesa_swizzle_string(srcReg->Swizzle,
549 srcReg->Negate, GL_FALSE))
[all...] |
| /external/llvm/lib/CodeGen/ |
| PHIElimination.cpp | 360 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg();
363 isImplicitlyDefined(SrcReg, MRI);
364 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
380 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg);
394 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg))
400 .addReg(SrcReg, 0, SrcSubReg);
404 // We only need to update the LiveVariables kill of SrcReg if this was the
405 // last PHI use of SrcReg to be lowered on this CFG edge and it is not live
408 !VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)] &&
409 !LV->isLiveOut(SrcReg, opBlock))
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFInstrInfo.cpp | 37 unsigned SrcReg, bool KillSrc) const {
38 if (BPF::GPRRegClass.contains(DestReg, SrcReg))
40 .addReg(SrcReg, getKillRegState(KillSrc));
47 unsigned SrcReg, bool IsKill, int FI,
56 .addReg(SrcReg, getKillRegState(IsKill))
|
| BPFInstrInfo.h | 34 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
38 MachineBasicBlock::iterator MBBI, unsigned SrcReg,
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.h | 44 * unsigned SrcReg, bool isKill, int FrameIndex,
53 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
55 virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/tests/ |
| radeon_compiler_util_tests.c | 53 &replace_inst.U.I.SrcReg[0],
54 &add_inst.U.I.SrcReg[0], &add_inst.U.I.SrcReg[1]);
|
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 271 unsigned DestReg, unsigned SrcReg,
273 if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
275 .addReg(SrcReg, getKillRegState(KillSrc));
276 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
278 .addReg(SrcReg, getKillRegState(KillSrc));
279 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg))
281 .addReg(SrcReg, getKillRegState(KillSrc));
288 unsigned SrcReg, bool isKill, int FI,
294 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
297 .addReg(SrcReg, getKillRegState(isKill))
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1InstrInfo.h | 42 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
46 unsigned SrcReg, bool isKill, int FrameIndex,
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| Thumb1InstrInfo.h | 42 unsigned DestReg, unsigned SrcReg,
46 unsigned SrcReg, bool isKill, int FrameIndex,
|
