| /external/vixl/test/aarch64/traces/ |
| sim-frintx-4s-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-frintz-2d-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-frintz-4s-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-ins-d-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-sqshl-h-2opimm-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-sqshlu-h-2opimm-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-sqxtn2-16b-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-sqxtun2-16b-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-uqshl-h-2opimm-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-uqxtn2-16b-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-xtn2-16b-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| /external/vixl/tools/ |
| clang_format.py | 3 # Copyright 2016, VIXL authors
|
| /external/vixl/src/aarch32/ |
| operands-aarch32.h | 1 // Copyright 2015, VIXL authors
33 namespace vixl { namespace
913 } // namespace vixl
|
| instructions-aarch32.h | 1 // Copyright 2015, VIXL authors
37 #include "utils-vixl.h"
38 #include "code-buffer-vixl.h"
48 namespace vixl { namespace
[all...] |
| /external/vixl/src/aarch64/ |
| operands-aarch64.h | 1 // Copyright 2016, VIXL authors
32 namespace vixl { namespace
959 } // namespace vixl::aarch64
|
| assembler-aarch64.h | 1 // Copyright 2015, VIXL authors
30 #include "../assembler-base-vixl.h"
31 #include "../code-generation-scopes-vixl.h"
32 #include "../globals-vixl.h"
33 #include "../invalset-vixl.h"
34 #include "../utils-vixl.h"
38 namespace vixl { namespace
371 // Allow VIXL to generate code that refers to absolute addresses. With this
376 // Allow VIXL to assume that the bottom 12 bits of the address will be
403 class Assembler : public vixl::internal::AssemblerBase
[all...] |
| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-operand-rn-t32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
485 } // namespace vixl
|
| test-assembler-cond-rd-rn-operand-rm-t32-rd-is-rn-is-sp-in-it-block.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
448 } // namespace vixl
|
| test-assembler-cond-rd-rn-t32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
468 } // namespace vixl
|
| test-assembler-cond-sp-sp-operand-imm7-t32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
368 } // namespace vixl
|
| test-simulator-cond-rd-operand-const-a32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
685 } // namespace vixl
|
| test-simulator-cond-rd-operand-const-t32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-operand-rn-a32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-simulator-cond-rd-operand-rn-t32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| /external/vixl/test/aarch64/examples/ |
| test-examples.cc | 1 // Copyright 2015, VIXL authors
38 using namespace vixl;
39 using namespace vixl::aarch64;
|
