| /external/vixl/test/aarch32/ |
| test-simulator-cond-rdlow-rnlow-rmlow-t32.cc | 1 // Copyright 2016, VIXL authors
113 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32-in-it-block.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-operand-rn-t32-low-registers-in-it-block.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-rn-operand-const-a32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-rn-operand-const-t32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-rn-operand-rm-a32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 1 // Copyright 2016, VIXL authors
47 namespace vixl { namespace
[all...] |
| /external/vixl/src/aarch64/ |
| constants-aarch64.h | 1 // Copyright 2015, VIXL authors
30 #include "../globals-vixl.h"
32 namespace vixl { namespace
[all...] |
| simulator-aarch64.h | 1 // Copyright 2015, VIXL authors
30 #include "../globals-vixl.h"
31 #include "../utils-vixl.h"
51 namespace vixl { namespace
[all...] |
| /external/vixl/test/aarch32/traces/ |
| assembler-cond-sp-sp-operand-imm7-t32-add.h | 1 // Copyright 2015, VIXL authors
|
| assembler-cond-sp-sp-operand-imm7-t32-sub.h | 1 // Copyright 2015, VIXL authors
|
| /external/vixl/test/aarch64/traces/ |
| sim-dup-4h-2opimm-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-fcvtn2-4s-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-fcvtn2-8h-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-fcvtxn2-4s-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-sqshl-s-2opimm-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-sqshlu-s-2opimm-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| sim-uqshl-s-2opimm-trace-aarch64.h | 1 // Copyright 2015, VIXL authors
|
| /external/vixl/tools/test_generator/ |
| parser.py | 1 # Copyright 2016, VIXL authors
|
| /art/compiler/optimizing/ |
| code_generator_vector_arm64.cc | 20 using namespace vixl::aarch64; // NOLINT(build/namespaces)
[all...] |
| /external/vixl/src/aarch32/ |
| disasm-aarch32.h | 1 // Copyright 2015, VIXL authors
38 namespace vixl { namespace
[all...] |
