| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-powerpc/ |
| vle-multiseg-1.d | 2 Elf file type is EXEC.*
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| vle-multiseg-2.d | 2 Elf file type is EXEC.*
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| vle-multiseg-3.d | 2 Elf file type is EXEC.*
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| vle-multiseg-4.d | 2 Elf file type is EXEC.*
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| vle-multiseg-5.d | 2 Elf file type is EXEC.*
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| vle-multiseg-6.d | 9 Elf file type is EXEC.*
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| /external/elfutils/backends/ |
| sparc_reloc.def | 29 /* NAME, REL|EXEC|DYN */
50 RELOC_TYPE (COPY, EXEC|DYN)
51 RELOC_TYPE (GLOB_DAT, EXEC|DYN)
52 RELOC_TYPE (JMP_SLOT, EXEC|DYN)
53 RELOC_TYPE (RELATIVE, EXEC|DYN)
73 RELOC_TYPE (GLOB_JMP, EXEC|DYN)
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| common-reloc.c | 73 #define EXEC (1 << (ET_EXEC - 1))
82 #undef EXEC
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| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-sh/ |
| fdpic-stack-default.d | 7 Elf file type is EXEC \(Executable file\)
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| fdpic-stack-set.d | 7 Elf file type is EXEC \(Executable file\)
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| fdpic-stack-size.d | 7 Elf file type is EXEC \(Executable file\)
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| tlsbin-2.d | 34 Elf file type is EXEC \(Executable file\)
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| /external/llvm/lib/Target/AMDGPU/ |
| SIWholeQuadMode.cpp | 22 /// S_MOV_B64 LiveMask, EXEC
23 /// S_WQM_B64 EXEC, EXEC
30 /// S_MOV_B64 EXEC, Tmp
167 // Handle export instructions with the exec mask valid flag set
343 AMDGPU::EXEC)
344 .addReg(AMDGPU::EXEC)
353 BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), AMDGPU::EXEC)
357 AMDGPU::EXEC)
358 .addReg(AMDGPU::EXEC);
[all...] |
| SILowerControlFlow.cpp | 17 /// by writting to the 64-bit EXEC register (each bit corresponds to a
19 /// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
21 /// EXEC to update the predicates.
33 /// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask
34 /// %SGPR0 = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
38 /// // EXEC are zero.
42 /// %SGPR0 = S_OR_SAVEEXEC_B64 %EXEC // Restore the exec mask for the Then block
43 /// %EXEC = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mas
[all...] |
| /toolchain/binutils/binutils-2.25/bfd/ |
| sparclynx.c | 123 #define SET_ARCH_MACH(ABFD, EXEC) \
124 NAME(lynx,set_arch_mach) (ABFD, N_MACHTYPE (EXEC)); \
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| aout-cris.c | 96 #define SET_ARCH_MACH(BFD, EXEC) \
97 MY_set_arch_mach (BFD, DEFAULT_ARCH, N_MACHTYPE (EXEC))
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| mipsbsd.c | 48 #define SET_ARCH_MACH(ABFD, EXEC) \
49 MY(set_arch_mach) (ABFD, N_MACHTYPE (EXEC)); \
392 0, /* text size includes exec header */
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| aoutf1.h | 158 #define SET_ARCH_MACH(ABFD, EXEC) \
159 NAME(sunos,set_arch_mach) (ABFD, N_MACHTYPE (EXEC)); \
487 so we are unable to synthesize an internal exec header.
489 which is the only thing needed from the internal exec header,
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| /external/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| fd2_program.c | 295 * EXEC ADDR(0x2) CNT(0x1)
314 cf = ir2_cf_create(so->ir, EXEC);
333 * EXEC ADDR(0x3) CNT(0x2)
337 * EXEC ADDR(0x5) CNT(0x1)
356 cf = ir2_cf_create(so->ir, EXEC);
369 cf = ir2_cf_create(so->ir, EXEC);
416 * EXEC ADDR(0x3) CNT(0x1)
420 * EXEC ADDR(0x4) CNT(0x1)
437 cf = ir2_cf_create(so->ir, EXEC);
444 cf = ir2_cf_create(so->ir, EXEC);
[all...] |
| ir-a2xx.c | 96 if ((cf->cf_type == EXEC) || (cf->cf_type == EXEC_END)) {
99 if (cf->exec.addr && (cf->exec.addr != addr))
100 WARN_MSG("invalid addr '%d' at CF %d", cf->exec.addr, i);
101 if (cf->exec.cnt && (cf->exec.cnt != cf->exec.instrs_count))
102 WARN_MSG("invalid cnt '%d' at CF %d", cf->exec.cnt, i);
104 for (j = cf->exec.instrs_count - 1; j >= 0; j--) {
105 struct ir2_instruction *instr = cf->exec.instrs[j]
[all...] |
| instr-a2xx.h | 173 EXEC = 1,
247 instr_cf_exec_t exec; member in union:PACKED
|
| disasm-a2xx.c | 477 return (cf->opc == EXEC) ||
503 printf(" ADDR(0x%x) CNT(0x%x)", cf->exec.address, cf->exec.count);
504 if (cf->exec.yeild)
506 if (cf->exec.vc)
507 printf(" VC(0x%x)", cf->exec.vc);
508 if (cf->exec.bool_addr)
509 printf(" BOOL_ADDR(0x%x)", cf->exec.bool_addr);
510 if (cf->exec.address_mode == ABSOLUTE_ADDR)
513 printf(" COND(%d)", cf->exec.condition)
[all...] |
| /hardware/interfaces/contexthub/1.0/ |
| types.hal | 170 EXEC = 1 << 2, // Executable
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| /external/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
| nvc0_transfer.c | 28 uint32_t exec = (1 << 20); local
50 exec |= NVC0_M2MF_EXEC_LINEAR_IN;
66 exec |= NVC0_M2MF_EXEC_LINEAR_OUT;
80 if (!(exec & NVC0_M2MF_EXEC_LINEAR_IN)) {
87 if (!(exec & NVC0_M2MF_EXEC_LINEAR_OUT)) {
98 BEGIN_NVC0(push, NVC0_M2MF(EXEC), 1);
99 PUSH_DATA (push, exec);
117 uint32_t exec; local
129 exec = 0x200 /* 2D_ENABLE */ | 0x6 /* UNK */;
134 exec |= 0x100; /* DST_MODE_2D_LINEAR *
[all...] |
| /external/llvm/lib/Target/AMDGPU/Disassembler/ |
| AMDGPUDisassembler.cpp | 423 case 126: return createRegOperand(EXEC);
|
