| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-xc16x/ |
| absrel.d | 12 408: e0 d6 mov r6,#0xd
|
| /external/libavc/encoder/arm/ |
| ih264e_half_pel.s | 99 vld1.8 {d5, d6, d7}, [r0], r2 @// Load row1
109 vext.8 d28, d5, d6, #5 @//extract a[5] (column1,row1)
111 vext.8 d27, d6, d7, #5 @//extract a[5] (column2,row1)
115 vaddl.u8 q8, d27, d6 @// a0 + a5 (column2,row1)
122 vext.8 d28, d5, d6, #2 @//extract a[2] (column1,row1)
124 vext.8 d27, d6, d7, #2 @//extract a[2] (column2,row1)
135 vext.8 d28, d5, d6, #3 @//extract a[3] (column1,row1)
137 vext.8 d27, d6, d7, #3 @//extract a[3] (column2,row1)
148 vext.8 d28, d5, d6, #1 @//extract a[1] (column1,row1)
150 vext.8 d27, d6, d7, #1 @//extract a[1] (column2,row1
[all...] |
| ih264e_fmt_conv.s | 294 vld4.8 {d4, d5, d6, d7}, [r8]! @// Load the 16 elements of row 2
298 vrhadd.u8 d2, d2, d6
322 vld4.8 {d4, d5, d6, d7}, [r8]! @// Load the 16 elements of row 2
325 vrhadd.u8 d2, d2, d6
|
| /external/libhevc/decoder/arm/ |
| ihevcd_itrans_recon_dc_luma.s | 98 vld1.8 d6,[r7],r2
110 vaddw.u8 q11,q0,d6
120 vqmovun.s16 d6,q11
130 vst1.u32 {d6},[r11],r3
|
| /external/llvm/test/MC/ARM/ |
| neon-minmax-encoding.s | 4 vmax.s16 d4, d5, d6
12 vmax.s16 d5, d6
36 @ CHECK: vmax.s16 d4, d5, d6 @ encoding: [0x06,0x46,0x15,0xf2]
43 @ CHECK: vmax.s16 d5, d5, d6 @ encoding: [0x06,0x56,0x15,0xf2]
66 vmin.s16 d4, d5, d6
74 vmin.s16 d5, d6
98 @ CHECK: vmin.s16 d4, d5, d6 @ encoding: [0x16,0x46,0x15,0xf2]
105 @ CHECK: vmin.s16 d5, d5, d6 @ encoding: [0x16,0x56,0x15,0xf2]
|
| neont2-minmax-encoding.s | 6 vmax.s16 d4, d5, d6
14 vmax.s16 d5, d6
38 @ CHECK: vmax.s16 d4, d5, d6 @ encoding: [0x15,0xef,0x06,0x46]
45 @ CHECK: vmax.s16 d5, d5, d6 @ encoding: [0x15,0xef,0x06,0x56]
68 vmin.s16 d4, d5, d6
76 vmin.s16 d5, d6
100 @ CHECK: vmin.s16 d4, d5, d6 @ encoding: [0x15,0xef,0x16,0x46]
107 @ CHECK: vmin.s16 d5, d5, d6 @ encoding: [0x15,0xef,0x16,0x56]
|
| neon-vld-vst-align.s | [all...] |
| basic-arm-instructions-v8.1a.s | 72 vqrdmlsh.s16 d7, d6, d5
73 //CHECK-V81aARM: vqrdmlsh.s16 d7, d6, d5 @ encoding: [0x15,0x7c,0x16,0xf3]
74 //CHECK-V81aTHUMB: vqrdmlsh.s16 d7, d6, d5 @ encoding: [0x16,0xff,0x15,0x7c]
76 //CHECK-V8: vqrdmlsh.s16 d7, d6, d5
|
| neon-vst-encoding.s | 62 vst3.16 {d6, d7, d8}, [r2]
66 vst3.i32 {d6, d8, d10}, [r5]
71 vst3.8 {d4, d6, d8}, [r9], r4
75 vst3.p8 {d6, d7, d8}, [r8]!
83 @ CHECK: vst3.16 {d6, d7, d8}, [r2] @ encoding: [0x4f,0x64,0x02,0xf4]
87 @ CHECK: vst3.32 {d6, d8, d10}, [r5] @ encoding: [0x8f,0x65,0x05,0xf4]
91 @ CHECK: vst3.8 {d4, d6, d8}, [r9], r4 @ encoding: [0x04,0x45,0x09,0xf4]
94 @ CHECK: vst3.8 {d6, d7, d8}, [r8]! @ encoding: [0x0d,0x64,0x08,0xf4]
156 vst2.32 {d6[0], d8[0]}, [r2:64]!
173 @ CHECK: vst2.32 {d6[0], d8[0]}, [r2:64]! @ encoding: [0x5d,0x69,0x82,0xf4
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/m68k/ |
| fido.s | 34 movec %d6,%cac
|
| /external/libavc/common/arm/ |
| ih264_inter_pred_luma_bilinear_a9q.s | 143 vaddl.u8 q12, d2, d6
172 vaddl.u8 q12, d2, d6
206 vaddl.u8 q12, d2, d6
233 vaddl.u8 q12, d2, d6
264 vld1.8 {d6}, [r1], r4 @// Load row2 ;src2
267 vaddl.u8 q12, d2, d6
310 vld1.8 {d6}, [r1], r4 @// Load row10 ;src2
313 vaddl.u8 q12, d2, d6
356 vld1.32 d6[0], [r1], r4 @// Load row2 ;src2
359 vaddl.u8 q12, d2, d6
[all...] |
| ih264_inter_pred_luma_vert_qpel_a9q.s | 134 vaddl.u8 q6, d4, d6 @ temp1 = src[2_0] + src[3_0]
144 vaddl.u8 q6, d6, d8
165 vaddl.u8 q10, d6, d0
179 vaddl.u8 q7, d6, d4
200 vaddl.u8 q7, d8, d6 @ temp = src[0_0] + src[5_0]
229 vld1.u32 d6, [r0], r2
231 vaddl.u8 q8, d1, d6
238 vaddl.u8 q5, d3, d6
245 vaddl.u8 q7, d5, d6
284 vld1.u32 d6, [r0], r
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/rx/ |
| or.d | 71 d6: 06 95 f0 3f or 252\[r15\]\.l, r0
77 f0: 06 d6 00 fe 7f or 65532\[r0\]\.uw, r0
78 f5: 06 d6 0f fe 7f or 65532\[r0\]\.uw, r15
87 120: 06 d6 f0 fe 7f or 65532\[r15\]\.uw, r0
88 125: 06 d6 ff fe 7f or 65532\[r15\]\.uw, r15
|
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_neon_Convolve.S | 64 d4, d5, d6, d7
71 vmlal.s16 q8, d6, d0[2]
80 vmlal.s16 q9, d6, d0[1]
133 vld1.16 {d4, d5, d6}, [r6]
255 vmlal.s16 q4, d22, d6[0]
261 vmlal.s16 q5, d23, d6[0]
|
| /external/libhevc/common/arm/ |
| ihevc_deblk_luma_vert.s | 149 vdup.32 d6,d1[0]
274 vaddl.u8 q13,d5,d6
291 vqadd.u8 d30,d6,d19
295 vqsub.u8 d31,d6,d19
398 vaddw.u8 q8,q0,d6
405 vmull.u8 q1,d6,d23
489 vaddl.u8 q8,d6,d2
523 vtrn.8 d6,d3
524 vst1.16 {d6[0]},[r12],r1
530 vst1.16 {d6[1]},[r12],r
[all...] |
| ihevc_inter_pred_filters_luma_vert_w16inp.s | 155 vld1.16 {d6},[r3],r2 @src_tmp3 = vld1_u8(pu1_src_tmp)@
159 vmlal.s16 q4,d6,d28 @mul_res1 = vmlal_u8(mul_res1, src_tmp3, coeffabs_6)@
174 vmlal.s16 q5,d6,d27 @mul_res2 = vmlal_u8(mul_res2, src_tmp3, coeffabs_5)@
186 vmlal.s16 q6,d6,d26
197 vmlal.s16 q7,d6,d25
204 vld1.16 {d6},[r3],r2 @src_tmp3 = vld1_u8(pu1_src_tmp)@
228 vmlal.s16 q4,d6,d28 @mul_res1 = vmlal_u8(mul_res1, src_tmp3, coeffabs_6)@
241 vmlal.s16 q5,d6,d27 @mul_res2 = vmlal_u8(mul_res2, src_tmp3, coeffabs_5)@
263 vmlal.s16 q6,d6,d26
284 vmlal.s16 q7,d6,d2
[all...] |
| ihevc_inter_pred_luma_vert_w16inp_w16out.s | 165 vld1.16 {d6},[r3],r2 @src_tmp3 = vld1_u8(pu1_src_tmp)@
169 vmlal.s16 q4,d6,d28 @mul_res1 = vmlal_u8(mul_res1, src_tmp3, coeffabs_6)@
184 vmlal.s16 q5,d6,d27 @mul_res2 = vmlal_u8(mul_res2, src_tmp3, coeffabs_5)@
196 vmlal.s16 q6,d6,d26
208 vmlal.s16 q7,d6,d25
215 vld1.16 {d6},[r3],r2 @src_tmp3 = vld1_u8(pu1_src_tmp)@
241 vmlal.s16 q4,d6,d28 @mul_res1 = vmlal_u8(mul_res1, src_tmp3, coeffabs_6)@
255 vmlal.s16 q5,d6,d27 @mul_res2 = vmlal_u8(mul_res2, src_tmp3, coeffabs_5)@
278 vmlal.s16 q6,d6,d26
300 vmlal.s16 q7,d6,d2
[all...] |
| ihevc_inter_pred_chroma_vert_w16inp.s | 145 vld1.16 {d6},[r0],r2
150 vmlal.s16 q4,d6,d14
151 vmlal.s16 q0,d6,d15
200 vld1.s16 {d6},[r0],r2
223 vmlal.s16 q12,d6,d15
257 vld1.s16 {d6},[r0],r2
277 vmlal.s16 q12,d6,d15
320 vld1.s16 {d6},[r0],r2
322 vmlal.s16 q12,d6,d15
|
| ihevc_inter_pred_chroma_vert_w16inp_w16out.s | 145 vld1.16 {d6},[r0],r2
150 vmlal.s16 q4,d6,d14
151 vmlal.s16 q0,d6,d15
204 vld1.s16 {d6},[r0],r2
221 vmlal.s16 q12,d6,d15
252 vld1.s16 {d6},[r0],r2
271 vmlal.s16 q12,d6,d15
310 vld1.s16 {d6},[r0],r2
312 vmlal.s16 q12,d6,d15
|
| ihevc_intra_pred_luma_vert.s | 227 vmov.i64 d6, #0x00000000000000ff
238 vbsl d6, d25, d16
243 vst1.8 {d6,d7}, [r5], r3
260 vmov.i64 d6, #0x00000000000000ff
276 vbsl d6, d25, d16
281 vst1.8 {d6,d7}, [r5], r3
290 vmov.i64 d6, #0x00000000000000ff
302 vbsl d6, d25, d16
306 vst1.8 {d6,d7}, [r5], r3
|
| ihevc_intra_pred_chroma_mode_18_34.s | 140 vld1.8 {d6,d7},[r8],r6
141 vst1.8 {d6,d7},[r10],r3
|
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| loopfilter_8_neon.asm | 47 vld1.u8 {d6}, [r2@64], r1 ; p0
126 vld1.u8 {d6}, [r2], r1
136 vtrn.32 d6, d18
139 vtrn.16 d4, d6
144 vtrn.8 d5, d6
221 ; d6 p0
238 vabd.u8 d21, d5, d6 ; m3 = abs(p1 - p0)
247 vabd.u8 d25, d6, d4 ; m7 = abs(p0 - p2)
255 vabd.u8 d24, d6, d7 ; m9 = abs(p0 - q0)
256 vabd.u8 d27, d3, d6 ; m10 = abs(p3 - p0
[all...] |
| /external/openssh/ |
| umac.c | 338 UINT32 d0,d1,d2,d3,d4,d5,d6,d7; local
346 d6 = LOAD_UINT32_LITTLE(d+6); d7 = LOAD_UINT32_LITTLE(d+7);
351 h += MUL64((k2 + d2), (k6 + d6));
371 UINT32 d0,d1,d2,d3,d4,d5,d6,d7; local
382 d6 = LOAD_UINT32_LITTLE(d+6); d7 = LOAD_UINT32_LITTLE(d+7);
392 h1 += MUL64((k2 + d2), (k6 + d6));
393 h2 += MUL64((k6 + d2), (k10 + d6));
418 UINT32 d0,d1,d2,d3,d4,d5,d6,d7; local
431 d6 = LOAD_UINT32_LITTLE(d+6); d7 = LOAD_UINT32_LITTLE(d+7);
443 h1 += MUL64((k2 + d2), (k6 + d6));
473 UINT32 d0,d1,d2,d3,d4,d5,d6,d7; local
[all...] |
| /external/boringssl/ios-arm/crypto/fipsmodule/ |
| armv4-mont.S | 235 vld1.32 {d4,d5,d6,d7}, [r3]!
247 vmlal.u32 q10,d29,d6[0]
249 vmlal.u32 q11,d29,d6[1]
295 vmlal.u32 q10,d29,d6[0]
297 vmlal.u32 q11,d29,d6[1]
363 vld1.32 {d4,d5,d6,d7},[r3]!
387 vmlal.u32 q10,d29,d6[0]
389 vmlal.u32 q11,d29,d6[1]
418 vmlal.u32 q11,d29,d6[0]
420 vmlal.u32 q12,d29,d6[1
[all...] |
| /external/boringssl/linux-arm/crypto/fipsmodule/ |
| armv4-mont.S | 232 vld1.32 {d4,d5,d6,d7}, [r3]!
244 vmlal.u32 q10,d29,d6[0]
246 vmlal.u32 q11,d29,d6[1]
292 vmlal.u32 q10,d29,d6[0]
294 vmlal.u32 q11,d29,d6[1]
360 vld1.32 {d4,d5,d6,d7},[r3]!
384 vmlal.u32 q10,d29,d6[0]
386 vmlal.u32 q11,d29,d6[1]
415 vmlal.u32 q11,d29,d6[0]
417 vmlal.u32 q12,d29,d6[1
[all...] |
