| /art/compiler/linker/arm64/ |
| relative_patcher_arm64.cc | 266 // LDR/STR 32-bit or 64-bit with imm12 == 0 (unset).
312 // Check that the next instruction matches the expected LDR.
317 // LDR (immediate) with correct base_reg.
326 // LDR (register) with the correct base_reg, size=10 (32-bit), option=011 (extend = LSL),
327 // and S=1 (shift amount = 2 for 32-bit version), i.e. LDR Wt, [Xn, Xm, LSL #2].
337 // LDR (immediate) with correct root_reg.
363 __ Ldr(ip0.W(), lock_word);
370 "Field and array LDR offsets must be the same to reuse the same code.");
371 // Adjust the return address back to the LDR (1 instruction; 2 for heap poisoning).
373 "Field LDR must be 1 instruction (4B) before the return address label;
[all...] |
| /external/vixl/test/aarch32/ |
| test-assembler-aarch32.cc | 1172 __ Ldr(r0, &l1);
1180 __ Ldr(r4, MemOperand(r4)); // Load the first 4 characters in r4.
1209 __ Ldr(r0, &l1);
1226 __ Ldr(r4, MemOperand(r4)); // Load the first 4 characters in r4.
1268 // (if the pool is not already emitted due to the Ldr).
1272 __ Ldr(r4, &big_literal);
1277 __ Ldr(r0, &l1);
1279 // Generate nops, in order to bring the checkpoints of the Ldr and Ldrd
1296 // rewind, or because Ldr reached its range.
[all...] |
| test-simulator-cond-rd-rn-rm-a32-ge.cc | 477 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr)));
489 __ Ldr(q_bit, MemOperand(input_ptr, offsetof(Inputs, qbit)));
496 __ Ldr(ge_bits, MemOperand(input_ptr, offsetof(Inputs, ge)));
499 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd)));
500 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn)));
501 __ Ldr(rm, MemOperand(input_ptr, offsetof(Inputs, rm)));
|
| test-simulator-cond-rd-rn-rm-a32-q.cc | 461 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr)));
473 __ Ldr(q_bit, MemOperand(input_ptr, offsetof(Inputs, qbit)));
480 __ Ldr(ge_bits, MemOperand(input_ptr, offsetof(Inputs, ge)));
483 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd)));
484 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn)));
485 __ Ldr(rm, MemOperand(input_ptr, offsetof(Inputs, rm)));
|
| test-simulator-cond-rd-rn-rm-a32-sel.cc | 454 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr)));
466 __ Ldr(q_bit, MemOperand(input_ptr, offsetof(Inputs, qbit)));
473 __ Ldr(ge_bits, MemOperand(input_ptr, offsetof(Inputs, ge)));
476 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd)));
477 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn)));
478 __ Ldr(rm, MemOperand(input_ptr, offsetof(Inputs, rm)));
|
| test-simulator-cond-rd-rn-rm-t32-ge.cc | 477 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr)));
489 __ Ldr(q_bit, MemOperand(input_ptr, offsetof(Inputs, qbit)));
496 __ Ldr(ge_bits, MemOperand(input_ptr, offsetof(Inputs, ge)));
499 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd)));
500 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn)));
501 __ Ldr(rm, MemOperand(input_ptr, offsetof(Inputs, rm)));
|
| test-simulator-cond-rd-rn-rm-t32-q.cc | 461 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr)));
473 __ Ldr(q_bit, MemOperand(input_ptr, offsetof(Inputs, qbit)));
480 __ Ldr(ge_bits, MemOperand(input_ptr, offsetof(Inputs, ge)));
483 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd)));
484 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn)));
485 __ Ldr(rm, MemOperand(input_ptr, offsetof(Inputs, rm)));
|
| test-simulator-cond-rd-rn-rm-t32-sel.cc | 454 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr)));
466 __ Ldr(q_bit, MemOperand(input_ptr, offsetof(Inputs, qbit)));
473 __ Ldr(ge_bits, MemOperand(input_ptr, offsetof(Inputs, ge)));
476 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd)));
477 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn)));
478 __ Ldr(rm, MemOperand(input_ptr, offsetof(Inputs, rm)));
|
| test-simulator-cond-rd-operand-const-a32.cc | 542 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr)));
546 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd)));
|
| test-simulator-cond-rd-operand-const-t32.cc | 657 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr)));
661 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd)));
[all...] |
| test-simulator-cond-rd-operand-imm16-t32.cc | 495 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr)));
499 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd)));
|
| test-simulator-cond-rd-operand-rn-a32.cc | 673 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr)));
677 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd)));
678 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn)));
[all...] |
| test-simulator-cond-rd-operand-rn-ror-amount-a32.cc | [all...] |
| test-simulator-cond-rd-operand-rn-ror-amount-t32.cc | [all...] |
| test-simulator-cond-rd-operand-rn-t32.cc | 673 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr)));
677 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd)));
678 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn)));
[all...] |
| test-simulator-rd-rn-rm-a32.cc | [all...] |
| test-simulator-rd-rn-rm-t32.cc | [all...] |
| /external/vixl/test/aarch64/ |
| test-simulator-aarch64.cc | 229 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, n_index_shift));
351 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift));
355 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift));
486 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift));
490 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift));
494 __ Ldr(fa, MemOperand(inputs_base, index_a, UXTW, index_shift));
633 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift));
637 __ Ldr(fm, MemOperand(inputs_base, index_m, UXTW, index_shift));
770 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, index_shift));
897 __ Ldr(fn, MemOperand(inputs_base, index_n, UXTW, n_index_shift))
[all...] |
| test-utils-aarch64.cc | 497 __ Ldr(dump2_base,
499 __ Ldr(dump2, MemOperand(dump2, dump2.GetCode() * kXRegSizeInBytes));
|
| /art/compiler/utils/arm/ |
| jni_macro_assembler_arm_vixl.cc | 156 ___ Ldr(mr, MemOperand(tr, Thread::IsGcMarkingOffset<kArmPointerSize>().Int32Value()));
663 ___ Ldr(temp,
690 ___ Ldr(dest.AsVIXLRegister(), MemOperand(base, offset));
694 ___ Ldr(dest.AsVIXLRegisterPairLow(), MemOperand(base, offset));
695 ___ Ldr(dest.AsVIXLRegisterPairHigh(), MemOperand(base, offset + 4));
|
| assembler_arm_vixl.cc | 329 ___ Ldr(dest, MemOperand(base, offset));
402 ___ Ldr(vixl32::Register(i), MemOperand(sp, stack_offset));
|
| /external/vixl/test/ |
| test-code-generation-scopes.cc | 392 __ Ldr(aarch64::x0, 0x1234567890abcdef);
463 __ Ldr(aarch64::x0, 0x1234567890abcdef);
740 __ Ldr(aarch64::x10, 0x1234567890abcdef);
748 // otherwise the `Ldr` will run out of range when we generate the `nop`
|
| /art/compiler/optimizing/ |
| optimizing_cfi_test.cc | 212 __ Ldr(r0, vixl32::MemOperand(r0));
|
| code_generator_vector_arm64.cc | [all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.cc | 139 masm_->ldr(xzr, static_cast<int>(pool_size / kWRegSizeInBytes));
[all...] |
