| /external/vixl/test/aarch32/ |
| test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | [all...] |
| test-simulator-cond-rd-rn-a32.cc | [all...] |
| test-simulator-cond-rd-rn-operand-const-a32.cc | [all...] |
| test-simulator-cond-rd-rn-operand-const-t32.cc | [all...] |
| test-simulator-cond-rd-rn-t32.cc | [all...] |
| test-simulator-cond-rdlow-rnlow-operand-immediate-t32.cc | [all...] |
| test-simulator-cond-rd-rn-operand-imm12-t32.cc | [all...] |
| test-simulator-cond-rd-memop-immediate-512-a32.cc | [all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceInstARM32.h | 396 Ldr,
[all...] |
| IceInstARM32.cpp | [all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/ |
| winternl.h | 70 PPEB_LDR_DATA Ldr;
[all...] |
| /art/compiler/optimizing/ |
| code_generator_arm_vixl.cc | 83 // Reference load (except object array loads) is using LDR Rt, [Rn, #offset] which can handle
[all...] |
| /external/vixl/src/aarch32/ |
| macro-assembler-aarch32.h | 760 void Ldr(Condition cond, Register rt, RawLiteral* literal) {
764 EmitLiteralCondRL<&Assembler::ldr> emit_helper(rt);
767 void Ldr(Register rt, RawLiteral* literal) { Ldr(al, rt, literal); }
851 // Generic Ldr(register, data)
852 void Ldr(Condition cond, Register rt, uint32_t v) {
858 EmitLiteralCondRL<&Assembler::ldr> emit_helper(rt);
862 void Ldr(Register rt, T v) {
863 Ldr(al, rt, v);
[all...] |
| /external/vixl/test/aarch64/ |
| test-disasm-aarch64.cc | 165 COMPARE(dci(0xb9400400), "ldr w0, [x0, #4]");
[all...] |
