| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 135 OperandVector &Operands, MCStreamer &Out,
142 bool parseParenSuffix(StringRef Name, OperandVector &Operands);
144 bool parseBracketSuffix(StringRef Name, OperandVector &Operands);
147 SMLoc NameLoc, OperandVector &Operands) override;
151 OperandMatchResultTy parseMemOperand(OperandVector &Operands);
153 matchAnyRegisterNameWithoutDollar(OperandVector &Operands,
155 OperandMatchResultTy matchAnyRegisterWithoutDollar(OperandVector &Operands,
157 OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
158 OperandMatchResultTy parseImm(OperandVector &Operands);
159 OperandMatchResultTy parseJumpTarget(OperandVector &Operands);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/VMCore/ |
| Metadata.cpp | 48 // Use CallbackVH to hold MDNode operands.
114 // Destroy the operands.
160 // critical code because it recursively visits all the MDNode's operands.
192 // isFunctionLocal bit because that's implied by the operands.
193 // Note that if the operands are later nulled out, the node will be
225 // Coallocate space for the node and Operands together, then placement new.
280 // isFunctionLocal bit because that's implied by the operands.
281 // Note that if the operands are later nulled out, the node will be
321 // If this node is already not being uniqued (because one of the operands
328 // this node to remove it, so we don't care what state the operands are in
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86OptimizeLEAs.cpp | 49 /// \brief Returns a hash table key based on memory operands of \p MI. The
53 /// \brief Returns true if two machine operands are identical and they are not
58 /// \brief Returns true if two address displacement operands are of the same
66 /// A key based on instruction's memory operands.
73 Operands[0] = Base;
74 Operands[1] = Scale;
75 Operands[2] = Index;
76 Operands[3] = Segment;
82 if (!isIdenticalOp(*Operands[i], *Other.Operands[i])
[all...] |
| /external/llvm/lib/Transforms/IPO/ |
| ArgumentPromotion.cpp | 21 // more than three operands to the function, because passing thousands of
22 // operands for a large array or structure is unprofitable! This limit can be
413 // This load is safe if any prefix of its operands is safe to load.
529 IndicesVector Operands;
532 Operands.clear();
538 Operands.push_back(0);
555 Operands.push_back(C->getSExtValue());
574 // is safe if Operands, or a prefix of Operands, is marked as safe.
575 if (!PrefixIn(Operands, SafeToUnconditionallyLoad)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/MC/MCDisassembler/ |
| EDInst.h | 12 // representation, individual tokens and operands for a single instruction.
59 /// string representation, as well as its operands and tokens
74 /// The order in which operands from the InstInfo's operand information appear
81 /// The instruction's operands
82 opvec_t Operands;
132 /// parseOperands - populates the Operands member of the instruction,
145 /// numOperands - returns the number of operands available to retrieve, or -1
|
| /external/swiftshader/third_party/LLVM/lib/Transforms/IPO/ |
| ArgumentPromotion.cpp | 21 // more than three operands to the function, because passing thousands of
22 // operands for a large array or structure is unprofitable! This limit can be
266 // This load is safe if any prefix of its operands is safe to load.
379 IndicesVector Operands;
383 Operands.clear();
389 Operands.push_back(0);
406 Operands.push_back(C->getSExtValue());
426 // is safe if Operands, or a prefix of Operands, is marked as safe.
427 if (!PrefixIn(Operands, SafeToUnconditionallyLoad)
[all...] |
| /external/swiftshader/third_party/LLVM/test/MC/X86/ |
| x86_operands.s | 30 # Indirect Memory Operands
|
| /prebuilts/clang/host/darwin-x86/clang-3957855/prebuilt_include/llvm/include/llvm/Analysis/ |
| MemorySSAUpdater.h | 148 MemoryAccess *tryRemoveTrivialPhi(MemoryPhi *Phi, RangeType &Operands);
|
| /prebuilts/clang/host/darwin-x86/clang-3960126/prebuilt_include/llvm/include/llvm/Analysis/ |
| MemorySSAUpdater.h | 148 MemoryAccess *tryRemoveTrivialPhi(MemoryPhi *Phi, RangeType &Operands);
|
| /prebuilts/clang/host/darwin-x86/clang-3977809/prebuilt_include/llvm/include/llvm/Analysis/ |
| MemorySSAUpdater.h | 148 MemoryAccess *tryRemoveTrivialPhi(MemoryPhi *Phi, RangeType &Operands);
|
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/Analysis/ |
| MemorySSAUpdater.h | 148 MemoryAccess *tryRemoveTrivialPhi(MemoryPhi *Phi, RangeType &Operands);
|
| /prebuilts/clang/host/linux-x86/clang-3957855/prebuilt_include/llvm/include/llvm/Analysis/ |
| MemorySSAUpdater.h | 148 MemoryAccess *tryRemoveTrivialPhi(MemoryPhi *Phi, RangeType &Operands);
|
| /prebuilts/clang/host/linux-x86/clang-3960126/prebuilt_include/llvm/include/llvm/Analysis/ |
| MemorySSAUpdater.h | 148 MemoryAccess *tryRemoveTrivialPhi(MemoryPhi *Phi, RangeType &Operands);
|
| /prebuilts/clang/host/linux-x86/clang-3977809/prebuilt_include/llvm/include/llvm/Analysis/ |
| MemorySSAUpdater.h | 148 MemoryAccess *tryRemoveTrivialPhi(MemoryPhi *Phi, RangeType &Operands);
|
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/Analysis/ |
| MemorySSAUpdater.h | 148 MemoryAccess *tryRemoveTrivialPhi(MemoryPhi *Phi, RangeType &Operands);
|
| /external/llvm/include/llvm/Analysis/ |
| TargetTransformInfoImpl.h | 106 ArrayRef<const Value *> Operands) {
109 for (unsigned Idx = 0, Size = Operands.size(); Idx != Size; ++Idx)
110 if (!isa<Constant>(Operands[Idx]))
437 ArrayRef<const Value *> Operands) {
453 auto GTI = gep_type_begin(PointeeType, AS, Operands);
454 for (auto I = Operands.begin(); I != Operands.end(); ++I, ++GTI) {
|
| ConstantFolding.h | 11 // operands are constants, for example "sub i32 1, 0" -> "1".
42 /// Note that this fails if not all of the operands are constant. Otherwise,
56 /// specified operands. If successful, the constant result is returned, if not,
66 /// specified operands. If successful, the constant result is returned, if not,
79 /// instruction (icmp/fcmp) with the specified operands. If it fails, it
80 /// returns a constant expression of the specified operands.
88 /// operands. If it fails, it returns a constant expression of the specified
89 /// operands.
99 /// instruction with the specified operands and indices. The constant result is
105 /// specified operands and indices. The constant result is returned i
[all...] |
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| FixedLenDecoderEmitter.cpp | 223 std::map<unsigned, std::vector<OperandInfo> > &Operands;
247 Operands(FC.Operands), Filters(FC.Filters),
257 AllInstructions(Insts), Opcodes(IDs), Operands(Ops), Filters(),
270 AllInstructions(Insts), Opcodes(IDs), Operands(Ops),
457 Owner->Operands,
490 Owner->Operands,
825 std::vector<OperandInfo>& InsnOperands = Operands[Opc];
874 std::vector<OperandInfo>& InsnOperands = Operands[Opc];
[all...] |
| CodeGenInstruction.cpp | 89 // If we have MIOpInfo, then we have #operands equal to number of entries
290 CodeGenInstruction::CodeGenInstruction(Record *R) : TheDef(R), Operands(R) {
305 isPredicable = Operands.isPredicable || R->getValueAsBit("isPredicable");
329 ParseConstraints(R->getValueAsString("Constraints"), Operands);
332 Operands.ProcessDisableEncoding(R->getValueAsString("DisableEncoding"));
455 // Handle "zero_reg" for optional def operands.
512 for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
515 if (ResultInst->Operands[i].getTiedRegister() != -1)
521 Record *InstOpRec = ResultInst->Operands[i].Rec;
522 unsigned NumSubOps = ResultInst->Operands[i].MINumOperands
[all...] |
| EDEmitter.cpp | 205 /// operands in the order they appear in the printed instruction. Then, for
212 /// into the operands present in the AsmString) or a number
214 /// @arg inst - The instruction to use when looking up the operands
225 for (operandIterator = awInst.Operands.begin();
226 operandIterator != awInst.Operands.end();
345 /// X86PopulateOperands - Handles all the operands in an X86 instruction, adding
357 unsigned int numOperands = inst.Operands.size();
360 const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
387 opIndex = inst.Operands.getOperandNamed(std::string(opName));
426 /// the appropriate flags to the instruction and its operands
[all...] |
| FixedLenDecoderEmitter.h | 73 std::map<unsigned, std::vector<OperandInfo> > Operands;
|
| X86RecognizableInstr.h | 61 /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
81 /// Indicates whether the instruction has FR operands - MOVs with FR operands
88 /// The operands of the instruction, as listed in the CodeGenInstruction.
89 /// They are not one-to-one with operands listed in the MCInst; for example,
90 /// memory operands expand to 5 operands in the MCInst
91 const std::vector<CGIOperandList::OperandInfo>* Operands;
113 /// instructions are pure intrinsics and use unencodable operands; many
138 /// prefix. If it does, 32-bit register operands sta
[all...] |
| /external/spirv-llvm/lib/SPIRV/libSPIRV/ |
| SPIRVType.h | 308 std::vector<SPIRVEntry*> Operands(2, ElemType);
309 Operands[1] = (SPIRVEntry*)getLength();
310 return Operands;
569 std::vector<SPIRVEntry*> Operands(MemberTypeIdVec.size());
571 Operands[I] = getEntry(MemberTypeIdVec[I]);
572 return Operands;
600 std::vector<SPIRVEntry*> Operands( 1 + ParamTypeVec.size(), ReturnType);
601 std::copy(ParamTypeVec.begin(), ParamTypeVec.end(), ++Operands.begin());
602 return Operands;
|
| /external/llvm/test/MC/X86/ |
| x86_operands.s | 30 # Indirect Memory Operands
|
| /external/llvm/utils/TableGen/ |
| X86RecognizableInstr.h | 62 /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set
94 /// The operands of the instruction, as listed in the CodeGenInstruction.
95 /// They are not one-to-one with operands listed in the MCInst; for example,
96 /// memory operands expand to 5 operands in the MCInst
97 const std::vector<CGIOperandList::OperandInfo>* Operands;
115 /// prefix. If it does, 32-bit register operands stay
130 /// If it is not, then 16-bit immediate operands stay 16-bit.
136 /// handles operands that are in the REG field of the ModR/M byte.
141 /// handles operands that are in the REG field of the ModR/M byte
[all...] |
