| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 111 SmallVectorImpl<MachineInstr*> &Outs);
363 SmallVectorImpl<MachineInstr*> &Outs) {
397 Outs.push_back(MI);
|
| ARMISelLowering.h | 637 const SmallVectorImpl<ISD::OutputArg> &Outs,
644 const SmallVectorImpl<ISD::OutputArg> &Outs,
648 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 67 SmallVector<ISD::OutputArg, 4> Outs;
69 Fn->getAttributes().getRetAttributes(), Outs, TLI);
72 Outs, Fn->getContext());
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.h | 471 const SmallVectorImpl<ISD::OutputArg> &Outs,
474 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| SystemZISelLowering.cpp | 801 static void VerifyVectorTypes(const SmallVectorImpl<ISD::OutputArg> &Outs) {
802 for (unsigned i = 0; i < Outs.size(); ++i)
803 VerifyVectorType(Outs[i].VT, Outs[i].ArgVT);
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.h | 119 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 226 const SmallVectorImpl<ISD::OutputArg> &Outs,
238 CCInfo.AnalyzeReturn(Outs, RetCC_Blackfin);
285 const SmallVectorImpl<ISD::OutputArg> &Outs,
298 CCInfo.AnalyzeCallOperands(Outs, CC_Blackfin);
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 275 const SmallVectorImpl<ISD::OutputArg> &Outs,
289 Outs, OutVals, Ins, dl, DAG, InVals);
385 const SmallVectorImpl<ISD::OutputArg> &Outs,
393 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) {
403 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430);
446 &Outs,
456 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 83 const SmallVectorImpl<ISD::OutputArg> &Outs,
97 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
352 const SmallVectorImpl<ISD::OutputArg> &Outs,
364 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
376 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
377 ISD::ArgFlagsTy Flags = Outs[i].Flags;
410 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86FastISel.cpp | 720 SmallVector<ISD::OutputArg, 4> Outs;
722 Outs, TLI);
728 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
761 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
767 if (Outs[0].Flags.isSExt())
772 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND :
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 81 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
[all...] |
| NVPTXISelLowering.h | 495 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 232 const SmallVectorImpl<ISD::OutputArg> &Outs,
245 CCInfo.AnalyzeCallOperands(Outs, CC_Alpha);
478 const SmallVectorImpl<ISD::OutputArg> &Outs,
486 switch (Outs.size()) {
493 EVT ArgVT = Outs[0].VT;
508 EVT ArgVT = Outs[0].VT;
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 197 const SmallVectorImpl<ISD::OutputArg> &Outs,
201 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
202 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
208 const SmallVectorImpl<ISD::OutputArg> &Outs,
221 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
293 const SmallVectorImpl<ISD::OutputArg> &Outs,
304 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
728 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
744 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 503 const SmallVectorImpl<ISD::OutputArg> &Outs,
507 const SmallVectorImpl<ISD::OutputArg> &Outs,
|
| MipsFastISel.cpp | [all...] |
| MipsISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeISelLowering.cpp | 685 const SmallVectorImpl<ISD::OutputArg> &Outs,
705 CCInfo.AnalyzeCallOperands(Outs, CC_MBlaze);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.h | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceCfg.cpp | 495 NodeList Outs = Node->getOutEdges();
496 Ice::RandomShuffle(Outs.begin(), Outs.end(),
498 for (CfgNode *Next : Outs) {
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 558 const SmallVectorImpl<ISD::OutputArg> &Outs,
570 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
661 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
671 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
695 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
697 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
708 Outs, OutVals, Ins, DAG);
735 ISD::ArgFlagsTy Flags = Outs[i].Flags
[all...] |
