| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 576 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
641 bool PPC::isAllNegativeZeroVector(SDNode *N) {
657 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
667 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 142 for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
192 SDNode* Node = Op.getNode();
251 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetInstrInfo.cpp | [all...] |
| ScheduleDAG.cpp | 57 const MCInstrDesc *ScheduleDAG::getNodeDesc(const SDNode *Node) const {
314 /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
|
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 466 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
576 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
655 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
682 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
724 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
[all...] |
| /external/llvm/utils/TableGen/ |
| DAGISelMatcherEmitter.cpp | 652 OS << "bool CheckNodePredicate(SDNode *Node,\n";
675 OS << "bool CheckComplexPattern(SDNode *Root, SDNode *Parent,\n";
677 OS << " SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) override {\n";
720 // FIXME: The node xform could take SDValue's instead of SDNode*'s.
725 Record *SDNode = Entry.first;
733 std::string ClassName = CGP.getSDNodeInfo(SDNode).getSDClassName();
734 if (ClassName == "SDNode")
735 OS << " SDNode *N = V.getNode();\n";
830 OS << "SDNode *SelectCode(SDNode *N) {\n"
[all...] |
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| DAGISelMatcherEmitter.cpp | 620 OS << "bool CheckNodePredicate(SDNode *Node, unsigned PredNo) const {\n";
639 OS << "bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,\n";
641 OS << " SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {\n";
684 // FIXME: The node xform could take SDValue's instead of SDNode*'s.
689 Record *SDNode = Entry.first;
697 std::string ClassName = CGP.getSDNodeInfo(SDNode).getSDClassName();
698 if (ClassName == "SDNode")
699 OS << " SDNode *N = V.getNode();\n";
793 OS << "SDNode *SelectCode(SDNode *N) {\n"
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 234 void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
658 TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const
718 ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const
764 SDNode *Node = Op.getNode();
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 195 void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
645 TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const
705 ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const
749 SDNode *Node = Op.getNode();
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 717 SDNode* N = Op.getNode();
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 595 SDNode* N = Op.getNode();
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| ScheduleDAG.cpp | 48 const MCInstrDesc *ScheduleDAG::getNodeDesc(const SDNode *Node) const {
288 /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.h | 381 void AssignOrderingToNode(const SDNode *Node);
|
| TargetLowering.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIInstrInfo.cpp | 38 static unsigned getNumOperandsNoGlue(SDNode *Node) {
45 static SDValue findChainOperand(SDNode *Load) {
53 static bool nodesHaveSameOperandValue(SDNode *N0, SDNode* N1, unsigned OpName) {
93 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
[all...] |
| R600ISelLowering.cpp | 828 void R600TargetLowering::ReplaceNodeResults(SDNode *N,
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| X86InstrInfo.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 537 void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
777 void AlphaTargetLowering::ReplaceNodeResults(SDNode *N,
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 48 static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
50 cl::desc("Enable Hexagon SDNode scheduling"));
608 /// being lowered. Returns a SDNode with the same number of values as the
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 616 // The caller promoted the argument, so insert an Assert?ext SDNode so we
[all...] |
