/bionic/libm/x86_64/ |
s_tan.S | 158 divsd %xmm5, %xmm6 465 divsd %xmm5, %xmm6 [all...] |
e_pow.S | 781 divsd %xmm0, %xmm1 [all...] |
/external/valgrind/memcheck/tests/amd64/ |
sse_memory.stdout.exp | [all...] |
sse_memory.c | 292 TEST_INSN( &AllMask, SD,divsd)
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ilp32/ |
x86-64-simd-intel.d | 73 [ ]*[a-f0-9]+: f2 0f 5e 00 divsd xmm0,QWORD PTR \[rax\] 192 [ ]*[a-f0-9]+: f2 0f 5e 00 divsd xmm0,QWORD PTR \[rax\]
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x86-64-simd-suffix.d | 73 [ ]*[a-f0-9]+: f2 0f 5e 00 divsd \(%rax\),%xmm0 192 [ ]*[a-f0-9]+: f2 0f 5e 00 divsd \(%rax\),%xmm0
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x86-64-simd.d | 73 [ ]*[a-f0-9]+: f2 0f 5e 00 divsd \(%rax\),%xmm0 192 [ ]*[a-f0-9]+: f2 0f 5e 00 divsd \(%rax\),%xmm0
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
simd-intel.d | 53 [ ]*[a-f0-9]+: f2 0f 5e 00 divsd xmm0,QWORD PTR \[eax\] 146 [ ]*[a-f0-9]+: f2 0f 5e 00 divsd xmm0,QWORD PTR \[eax\]
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sse2avx.s | 481 divsd %xmm4,%xmm6 482 divsd (%ecx),%xmm6 1142 divsd xmm6,xmm4 1143 divsd xmm6,QWORD PTR [ecx]
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x86-64-simd-intel.d | 73 [ ]*[a-f0-9]+: f2 0f 5e 00 divsd xmm0,QWORD PTR \[rax\] 192 [ ]*[a-f0-9]+: f2 0f 5e 00 divsd xmm0,QWORD PTR \[rax\]
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x86-64-simd-suffix.d | 73 [ ]*[a-f0-9]+: f2 0f 5e 00 divsd \(%rax\),%xmm0 192 [ ]*[a-f0-9]+: f2 0f 5e 00 divsd \(%rax\),%xmm0
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x86-64-simd.d | 72 [ ]*[a-f0-9]+: f2 0f 5e 00 divsd \(%rax\),%xmm0 191 [ ]*[a-f0-9]+: f2 0f 5e 00 divsd \(%rax\),%xmm0
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x86-64-sse2avx.s | 505 divsd %xmm4,%xmm6 506 divsd (%rcx),%xmm6 1209 divsd xmm6,xmm4 1210 divsd xmm6,QWORD PTR [rcx]
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/art/compiler/utils/x86_64/ |
assembler_x86_64.h | 441 void divsd(XmmRegister dst, XmmRegister src); 442 void divsd(XmmRegister dst, const Address& src); [all...] |
assembler_x86_64.cc | 775 void X86_64Assembler::divsd(XmmRegister dst, XmmRegister src) { function in class:art::x86_64::X86_64Assembler 785 void X86_64Assembler::divsd(XmmRegister dst, const Address& src) { function in class:art::x86_64::X86_64Assembler [all...] |
assembler_x86_64_test.cc | [all...] |
/external/swiftshader/third_party/LLVM/test/MC/X86/ |
x86-32-coverage.s | 1166 // CHECK: divsd %xmm5, %xmm5 1167 divsd %xmm5,%xmm5 [all...] |
/external/v8/src/ia32/ |
assembler-ia32.h | [all...] |
/external/llvm/test/MC/X86/ |
x86-32-coverage.s | [all...] |
/bionic/libm/x86/ |
e_pow.S | 831 divsd %xmm0, %xmm1 [all...] |
/external/v8/src/x64/ |
macro-assembler-x64.h | [all...] |
assembler-x64.h | [all...] |
/art/compiler/utils/x86/ |
assembler_x86.cc | 699 void X86Assembler::divsd(XmmRegister dst, XmmRegister src) { function in class:art::x86::X86Assembler 708 void X86Assembler::divsd(XmmRegister dst, const Address& src) { function in class:art::x86::X86Assembler [all...] |
/external/v8/src/compiler/ia32/ |
code-generator-ia32.cc | 218 __ divsd(result_, result_); [all...] |
/external/libvpx/libvpx/third_party/x86inc/ |
x86inc.asm | [all...] |