| /device/linaro/bootloader/edk2/MdePkg/Library/BaseLib/Ipf/ |
| LongJmp.s | 107 ldf.fill.nt1 f30 = [r10], -0x10
|
| SetJmp.s | 99 stf.spill.nta [in0] = f30, 0x10
|
| /external/llvm/test/MC/ELF/ |
| cfi.s | 179 f30: label
|
| /external/llvm/test/MC/Mips/mips2/ |
| invalid-mips32.s | 34 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
35 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| valid.s | 41 c.sf.d $f30,$f0
95 mul.s $f30,$f10,$f2
174 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
|
| invalid-mips4.s | 15 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
64 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
65 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| invalid-mips5.s | 15 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
62 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
63 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
| /external/llvm/test/MC/PowerPC/ |
| ppc64-regs.s | 70 #CHECK: .cfi_offset f30, 548
187 .cfi_offset f30,548
|
| /external/swiftshader/third_party/LLVM/test/MC/ELF/ |
| cfi.s | 179 f30: label
|
| /external/syslinux/gnu-efi/gnu-efi-3.0/inc/protocol/ia64/ |
| eficontext.h | 129 UINT64 f30[2];
member in struct:__anon34311
|
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/ |
| setjmp.s | 100 stf.spill.nta [in0] = f30, 0x10
|
| /external/llvm/test/MC/Mips/mips1/ |
| invalid-mips4.s | 17 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
67 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
68 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
93 trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips5.s | 17 cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
66 movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
67 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
87 trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips1.s | 13 c.sf.d $f30,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips32.s | 22 movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips1.s | 16 c.sf.d $f30,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/v8/src/compiler/ |
| c-linkage.cc | 99 f20.bit() | f22.bit() | f24.bit() | f26.bit() | f28.bit() | f30.bit()
110 f20.bit() | f22.bit() | f24.bit() | f26.bit() | f28.bit() | f30.bit()
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i860/ |
| pfam.d | 44 88: 8b ec df 4b m12ttpa.sd %f29,%f30,%f31
51 a4: 8d f5 02 48 m12tpm.dd %f30,%f0,%f2
126 1d0: 8b ee df 4b d.m12ttpa.sd %f29,%f30,%f31
140 208: 8d f7 02 48 d.m12tpm.dd %f30,%f0,%f2
|
| pfsm.d | 44 88: 9b ec df 4b m12ttsa.sd %f29,%f30,%f31
51 a4: 9d f5 02 48 m12tsm.dd %f30,%f0,%f2
126 1d0: 9b ee df 4b d.m12ttsa.sd %f29,%f30,%f31
140 208: 9d f7 02 48 d.m12tsm.dd %f30,%f0,%f2
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sparc/ |
| hpcvis3.s | 30 fumsubd %f24, %f26, %f28, %f30
|
| /external/llvm/test/MC/Mips/mips3/ |
| valid.s | 42 c.sf.d $f30,$f0
56 cvt.s.l $f15,$f30
155 mul.s $f30,$f10,$f2
240 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
|
| /external/llvm/test/MC/Mips/mips32/ |
| valid.s | 46 c.sf.d $f30,$f0
110 movt.s $f30,$f2,$fcc1
123 mul.s $f30,$f10,$f2
204 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 46 c.sf.d $f30,$f0
62 cvt.s.l $f15,$f30
195 movt.s $f30,$f2,$fcc1
210 mul.s $f30,$f10,$f2
316 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 46 c.sf.d $f30,$f0
62 cvt.s.l $f15,$f30
195 movt.s $f30,$f2,$fcc1
210 mul.s $f30,$f10,$f2
316 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 46 c.sf.d $f30,$f0
62 cvt.s.l $f15,$f30
196 movt.s $f30,$f2,$fcc1
211 mul.s $f30,$f10,$f2
317 trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
|
