| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-tic6x.c | 5260 int reg2; local
[all...] |
| tc-metag.c | 383 /* Return TRUE if REG1 and REG2 are in paired units. */
385 is_unit_pair (const metag_reg *reg1, const metag_reg *reg2)
388 (reg2->unit == UNIT_A1)) ||
390 (reg2->unit == UNIT_A0)) ||
392 (reg2->unit == UNIT_D1)) ||
394 (reg2->unit == UNIT_D0)))
400 /* Return TRUE if REG1 and REG2 form a register pair. */
402 is_reg_pair (const metag_reg *reg1, const metag_reg *reg2)
405 reg2->unit == UNIT_FX &&
406 reg2->no == reg1->no + 1
[all...] |
| /external/v8/src/mips/ |
| macro-assembler-mips.cc | [all...] |
| macro-assembler-mips.h | 97 Register reg2 = no_reg,
103 bool AreAliased(Register reg1, Register reg2, Register reg3 = no_reg,
254 void Swap(Register reg1, Register reg2, Register scratch = no_reg);
[all...] |
| /external/v8/src/arm64/ |
| assembler-arm64.h | 348 Register reg2 = NoReg,
356 const CPURegister& reg2,
369 const CPURegister& reg2,
388 CPURegister reg2 = NoCPUReg,
391 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
393 DCHECK(AreSameSizeAndType(reg1, reg2, reg3, reg4));
[all...] |
| assembler-arm64.cc | 212 Register GetAllocatableRegisterThatIsNotOneOf(Register reg1, Register reg2,
214 CPURegList regs(reg1, reg2, reg3, reg4);
227 bool AreAliased(const CPURegister& reg1, const CPURegister& reg2,
237 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
264 bool AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2,
270 match &= !reg2.IsValid() || reg2.IsSameSizeAndType(reg1);
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64_test.cc | 336 DriverStr(RepeatFFF(&mips64::Mips64Assembler::AddS, "add.s ${reg1}, ${reg2}, ${reg3}"), "add.s");
340 DriverStr(RepeatFFF(&mips64::Mips64Assembler::AddD, "add.d ${reg1}, ${reg2}, ${reg3}"), "add.d");
344 DriverStr(RepeatFFF(&mips64::Mips64Assembler::SubS, "sub.s ${reg1}, ${reg2}, ${reg3}"), "sub.s");
348 DriverStr(RepeatFFF(&mips64::Mips64Assembler::SubD, "sub.d ${reg1}, ${reg2}, ${reg3}"), "sub.d");
352 DriverStr(RepeatFFF(&mips64::Mips64Assembler::MulS, "mul.s ${reg1}, ${reg2}, ${reg3}"), "mul.s");
356 DriverStr(RepeatFFF(&mips64::Mips64Assembler::MulD, "mul.d ${reg1}, ${reg2}, ${reg3}"), "mul.d");
360 DriverStr(RepeatFFF(&mips64::Mips64Assembler::DivS, "div.s ${reg1}, ${reg2}, ${reg3}"), "div.s");
364 DriverStr(RepeatFFF(&mips64::Mips64Assembler::DivD, "div.d ${reg1}, ${reg2}, ${reg3}"), "div.d");
368 DriverStr(RepeatFF(&mips64::Mips64Assembler::SqrtS, "sqrt.s ${reg1}, ${reg2}"), "sqrt.s");
372 DriverStr(RepeatFF(&mips64::Mips64Assembler::SqrtD, "sqrt.d ${reg1}, ${reg2}"), "sqrt.d")
[all...] |
| /external/v8/src/crankshaft/x87/ |
| lithium-codegen-x87.h | 86 void X87LoadForUsage(X87Register reg1, X87Register reg2);
|
| /external/v8/src/ppc/ |
| macro-assembler-ppc.h | 59 Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2 = no_reg,
67 bool AreAliased(Register reg1, Register reg2, Register reg3 = no_reg,
[all...] |
| macro-assembler-ppc.cc | [all...] |
| /external/valgrind/coregrind/m_debuginfo/ |
| readdwarf.c | 2894 Int off, reg, reg2, len, j; local
3306 Int off, coff, reg, reg2, len; local
[all...] |
| /external/v8/src/full-codegen/arm64/ |
| full-codegen-arm64.cc | 66 void EmitJumpIfEitherNotSmi(Register reg1, Register reg2, Label* target) {
69 __ Orr(temp, reg1, reg2);
[all...] |
| /external/v8/src/full-codegen/mips/ |
| full-codegen-mips.cc | [all...] |
| /external/v8/src/full-codegen/mips64/ |
| full-codegen-mips64.cc | [all...] |
| /external/v8/src/full-codegen/ppc/ |
| full-codegen-ppc.cc | [all...] |
| /external/v8/src/full-codegen/s390/ |
| full-codegen-s390.cc | [all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| msp430-decode.opc | 72 msp430->op[n].reg2 = r2, \
|
| /external/v8/src/mips64/ |
| macro-assembler-mips64.h | 103 Register reg2 = no_reg,
109 bool AreAliased(Register reg1, Register reg2, Register reg3 = no_reg,
283 void Swap(Register reg1, Register reg2, Register scratch = no_reg);
[all...] |
| macro-assembler-mips64.cc | [all...] |
| /art/runtime/interpreter/mterp/out/ |
| mterp_arm64.S | 306 .macro SAVE_TWO_REGS reg1, reg2, offset
307 stp \reg1, \reg2, [sp, #(\offset)]
309 .cfi_rel_offset \reg2, (\offset) + 8
315 .macro RESTORE_TWO_REGS reg1, reg2, offset
316 ldp \reg1, \reg2, [sp, #(\offset)]
318 .cfi_restore \reg2
324 .macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment
325 stp \reg1, \reg2, [sp, #-(\frame_adjustment)]!
328 .cfi_rel_offset \reg2, 8
334 .macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustmen
[all...] |
| /external/vixl/src/aarch64/ |
| assembler-aarch64.cc | [all...] |
| /art/compiler/optimizing/ |
| code_generator_x86_64.h | 143 void Exchange64(CpuRegister reg1, CpuRegister reg2);
|
| /external/libvpx/libvpx/third_party/libyuv/include/libyuv/ |
| row.h | 519 #define VMEMOPREG(opcode, offset, base, index, scale, reg1, reg2) \
522 #opcode " (%%r15,%%r14),%%" #reg1 ",%%" #reg2 "\n" \
547 #define VMEMOPREG(opcode, offset, base, index, scale, reg1, reg2) \
549 #reg2 "\n"
[all...] |
| /external/pcre/dist2/src/sljit/ |
| sljitNativeARM_T2_32.c | 63 #define IS_2_LO_REGS(reg1, reg2) \
64 (reg_map[reg1] <= 7 && reg_map[reg2] <= 7)
65 #define IS_3_LO_REGS(reg1, reg2, reg3) \
66 (reg_map[reg1] <= 7 && reg_map[reg2] <= 7 && reg_map[reg3] <= 7)
[all...] |
| /external/v8/src/s390/ |
| macro-assembler-s390.h | 66 Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2 = no_reg,
73 bool AreAliased(Register reg1, Register reg2, Register reg3 = no_reg,
[all...] |
