| /prebuilts/ndk/r11/platforms/android-19/arch-arm/usr/include/asm/arch/ |
| mux.h | 32 #define MUX_CFG_24XX(desc, reg_offset, mode, pull_en, pull_mode, dbg) { .name = desc, .debug = dbg, .mux_reg = reg_offset, .mask = mode, .pull_val = pull_en, .pu_pd_val = pull_mode, },
|
| /prebuilts/ndk/r11/platforms/android-3/arch-arm/usr/include/asm/arch/ |
| mux.h | 32 #define MUX_CFG_24XX(desc, reg_offset, mode, pull_en, pull_mode, dbg) { .name = desc, .debug = dbg, .mux_reg = reg_offset, .mask = mode, .pull_val = pull_en, .pu_pd_val = pull_mode, },
|
| /prebuilts/ndk/r11/platforms/android-4/arch-arm/usr/include/asm/arch/ |
| mux.h | 32 #define MUX_CFG_24XX(desc, reg_offset, mode, pull_en, pull_mode, dbg) { .name = desc, .debug = dbg, .mux_reg = reg_offset, .mask = mode, .pull_val = pull_en, .pu_pd_val = pull_mode, },
|
| /prebuilts/ndk/r11/platforms/android-5/arch-arm/usr/include/asm/arch/ |
| mux.h | 32 #define MUX_CFG_24XX(desc, reg_offset, mode, pull_en, pull_mode, dbg) { .name = desc, .debug = dbg, .mux_reg = reg_offset, .mask = mode, .pull_val = pull_en, .pu_pd_val = pull_mode, },
|
| /prebuilts/ndk/r11/platforms/android-8/arch-arm/usr/include/asm/arch/ |
| mux.h | 32 #define MUX_CFG_24XX(desc, reg_offset, mode, pull_en, pull_mode, dbg) { .name = desc, .debug = dbg, .mux_reg = reg_offset, .mask = mode, .pull_val = pull_en, .pu_pd_val = pull_mode, },
|
| /prebuilts/ndk/r11/platforms/android-9/arch-arm/usr/include/asm/arch/ |
| mux.h | 32 #define MUX_CFG_24XX(desc, reg_offset, mode, pull_en, pull_mode, dbg) { .name = desc, .debug = dbg, .mux_reg = reg_offset, .mask = mode, .pull_val = pull_en, .pu_pd_val = pull_mode, },
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_vec4_visitor.cpp | 1481 int reg_offset = base_offset + orig_src.offset \/ REG_SIZE; local
1510 int reg_offset = base_offset + inst->dst.offset \/ REG_SIZE; local
1726 int reg_offset = base_offset + src.offset \/ 16; local
[all...] |
| brw_vec4.h | 292 src_reg *reladdr, int reg_offset);
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-tic6x.h | 64 offsetT reg_offset[TIC6X_NUM_UNWIND_REGS]; member in struct:tic6x_unwind_info
|
| tc-tic6x.c | [all...] |
| /external/mesa3d/src/amd/common/ |
| ac_debug.c | 132 unsigned reg_offset)
134 unsigned reg = (ib[1] << 2) + reg_offset;
|
| /hardware/qcom/msm8x84/kernel-headers/media/ |
| msmb_isp.h | 326 uint32_t reg_offset; member in struct:msm_vfe_reg_rw_info
332 uint32_t reg_offset; member in struct:msm_vfe_reg_mask_info
|
| /hardware/qcom/msm8x84/original-kernel-headers/media/ |
| msmb_isp.h | 294 uint32_t reg_offset; member in struct:msm_vfe_reg_rw_info
300 uint32_t reg_offset; member in struct:msm_vfe_reg_mask_info
|
| /hardware/qcom/msm8994/kernel-headers/media/ |
| msmb_isp.h | 439 uint32_t reg_offset; member in struct:msm_vfe_reg_rw_info
445 uint32_t reg_offset; member in struct:msm_vfe_reg_mask_info
|
| /hardware/qcom/msm8994/original-kernel-headers/media/ |
| msmb_isp.h | 410 uint32_t reg_offset; member in struct:msm_vfe_reg_rw_info
416 uint32_t reg_offset; member in struct:msm_vfe_reg_mask_info
|
| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| amdgpu_winsys.c | 460 unsigned reg_offset,
465 return amdgpu_read_mm_registers(ws->dev, reg_offset / 4, num_registers,
|
| /external/mesa3d/src/gallium/winsys/radeon/drm/ |
| radeon_drm_winsys.c | 665 unsigned reg_offset,
672 uint32_t reg = reg_offset + i*4;
|
| /hardware/qcom/msm8996/kernel-headers/media/ |
| msmb_isp.h | 482 uint32_t reg_offset; member in struct:msm_vfe_reg_rw_info
489 uint32_t reg_offset; member in struct:msm_vfe_reg_mask_info
[all...] |
| /hardware/qcom/msm8996/original-kernel-headers/media/ |
| msmb_isp.h | 448 uint32_t reg_offset; member in struct:msm_vfe_reg_rw_info
454 uint32_t reg_offset; member in struct:msm_vfe_reg_mask_info
|
| /hardware/qcom/msm8998/kernel-headers/media/ |
| msmb_isp.h | 515 uint32_t reg_offset; member in struct:msm_vfe_reg_rw_info
521 uint32_t reg_offset; member in struct:msm_vfe_reg_mask_info
[all...] |
| /hardware/qcom/msm8998/original-kernel-headers/media/ |
| msmb_isp.h | 478 uint32_t reg_offset; member in struct:msm_vfe_reg_rw_info
484 uint32_t reg_offset; member in struct:msm_vfe_reg_mask_info
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| radeon_winsys.h | 751 bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
|
| /external/mesa3d/src/gallium/drivers/r600/sb/ |
| sb_ir.h | 606 int reg_offset = select.sel() - array->base_gpr.sel(); local
608 reg_offset += rel->get_const_value().i;
609 return array->gpr + (reg_offset << 2);
|
| /system/core/libpixelflinger/codeflinger/ |
| Arm64Assembler.cpp | 617 *mPC++ = A64_LDRSTR_Wm_SXTW_0(op, size, Rd, Rn, mAddrMode.reg_offset);
934 mAddrMode.reg_offset = Rm;
972 mAddrMode.reg_offset = Rm;
[all...] |
| /external/elfutils/libdw/ |
| cfi.c | 366 fs->regs[regno].rule = reg_offset;
|
